Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
Opcode is fetched during the interrupt acknowledge cycle
in ITC will reveal whether the restart at physical
address 00000H was caused by RESET or TRAP.
for INT when Mode 0 is used.
0
When
a
TRAP
interrupt
occurs,
the
All TRAP interrupts occur after fetching an undefined sec-
ond Opcode byte following one of the “prefix” Opcodes
CBH, DDH, EDH, or FDH, or after fetching an undefined
third Opcode byte following one of the “double prefix” Op-
codes DDCBH or FDCBH.
Z80180/Z8S180/Z8L180 operates as follows:
1. The TRAP bit in the Interrupt TRAP/Control (ITC)
register is set to 1.
2. The current PC (Program Counter) value, reflecting
the location of the undefined Opcode, is saved on the
stack.
The state of the Undefined Fetch Object (UFO) bit in ITC
allows TRAP software to correctly “adjust” the stacked PC,
depending on whether the second or third byte of the Op-
code generated the TRAP. If UFO=0, the starting address
of the invalid instruction is equal to the stacked PC-1. If
UFO=1, the starting address of the invalid instruction is
equal to the stacked PC-2.
3. The Z80180/Z8S180/Z8L180 vectors to logical
address 0. Note that if logical address 0000H is
mapped to physical address 00000H, the vector is the
same as for RESET. In this case, testing the TRAP bit
Restart
from 0000H
Opcode
PC Stacking
Fetch Cycle
2nd Opcode
Fetch Cycle
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
2
3
1
2
3
TP
i
i
i
i
i
1
2
3
1
2
3
1
φ
A -A (A )
0000H
PC
SP-1
SP-2
PC
0
18
19
D -D
PC
0
7
H
L
Undefined
Opcode
M1
MREQ
RD
WR
nd
Figure 76. TRAP Timing-2 Opcode Undefined
1-60
P R E L I M I N A R Y
DS971800401
ZILOG [ ZILOG, INC. ]
