Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
Table 14. DRAM Refresh Intervals
Time Interval
Insertion
CYC1
CYC0
Interval
Ø: 10 MHz
8 MHz
6 MHz
4 MHz
2.5 MHz
0
0
1
1
0
1
0
1
10 states
20 states
40 states
80 states
(1.0 µs)*
(2.0 µs)*
(4.0 µs)*
(8.0 µs)*
(1.25 µs)*
(2.5 µs)*
(5.0 µs)*
(10.0 µs)*
1.66 µs
3.3 µs
2.5 µs
5.0 µs
4.0 µs
8.0 µs
6.6 µs
10.0 µs
20.0 µs
16.0 µs
32.0 µs
13.3 µs
Note: *calculated interval
Refresh Control and Reset. After RESET, based on the
initialized value of RCR, refresh cycles will occur with an
interval of 10 clock cycles and be 3 clock cycles in dura-
tion.
which the first refresh cycle occurs after the
Z80180/Z8S180/Z8L180 re-acquires the bus depends
on the refresh timer and has no timing relationship with
the bus exchange.
Dynamic RAM Refresh Operation
3. Refresh cycles are suppressed during SLEEP mode.
If a refresh cycle is requested during SLEEP mode,
the refresh cycle request is internally “latched” (until
replaced with the next refresh request). The “latched”
refresh cycle is inserted at the end of the first machine
cycle after SLEEP mode is exited. After this initial
cycle, the time at which the next refresh cycle occurs
depends on the refresh time and has no relationship
with the exit from SLEEP mode.
1. Refresh Cycle insertion is stopped when the CPU is in
the following states:
a. During RESET
b. When the bus is released in response to
BUSREQ.
c. During SLEEP mode.
d. During WAIT states.
4. The refresh address is incremented by one for each
successful refresh cycle, not for each refresh. Thus,
independent of the number of “missed” refresh
requests, each refresh bus cycle will use a refresh
address incremented by one from that of the previous
refresh bus cycles.
2. Refresh cycles are suppressed when the bus is
released in response to BUSREQ. However, the
refresh timer continues to operate. Thus, the time at
MMU COMMON BASE REGISTER
Mnemonic CBR
MMU Common Base Register (CBR). CBR specifies the
base address (on 4 KB boundaries) used to generate a 20-
bit physical address for Common Area 1 accesses. All bits
of CBR are reset to 0 during RESET.
Address 38
5
4
3
2
1
0
7
6
Bit
CB7
R/W
CB6
R/W
CB5
R/W
CB4
R/W
CB3
R/W
CB0
R/W
CB2
R/W
CB1
R/W
Figure 79. MMU Common Base Register (BBR: I/O Address = 38H)
1-62
P R E L I M I N A R Y
DS971800401
ZILOG [ ZILOG, INC. ]
