Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
With one-wait-state I/O cycles (the fastest possible except
for the ASCIs), it is unlikely that an output device will be
able to update its Request in time, and edge sense is re-
quired.
modifier for channel 1 memory to/from I/O transfer modes.
DIM1 and DIM0 are cleared to 0 during RESET.
Table 13. Channel 1 Transfer Mode
1
Address
DIM1, DIM0: DMA Channel 1 I/O and Memory Mode
DIM1 DMI0 Transfer Mode Increment/Decrement
(bits 1-0). Specifies the source/destination and address
0
0
1
1
0
1
0
1
Memory→I/O
Memory→I/O
I/O→Memory
I/O→Memory
MAR1 +1, IAR1 fixed
MAR1–1, IAR1 fixed
IAR1 fixed, MAR1 + 1
IAR1 fixed, MAR1 –1
INTERRUPT VECTOR LOW REGISTER
Mnemonic: IL
Bits 7-5 of IL are used as bits 7-5 of the synthesized inter-
rupt vector during interrupts for the INT1 and INT2 pins
and for the DMAs, ASCIs, PRTs, and CSI/O. These three
bits are cleared to 0 during Reset (Figure 75).
Address 33
4
––
1
7
6
2
0
5
3
Bit
IL 6
IL 7
R/W
IL 5
––
––
––
––
R/W R/W
Programmable
Interrupt Source Dependent Code
Figure 75. Interrupt Vector Low Register (IL: I/O Address = 33H)
INT/TRAP CONTROL REGISTER
Mnemonics ITC
the starting address of the undefined instruction. This is
necessary since the TRAP may occur on either the second
or third byte of the Opcode. UFO allows the stacked PC
value to be correctly adjusted. If UFO = 0, the first Opcode
should be interpreted as the stacked PC-1. If UFO = 1, the
first Opcode address is stacked PC-2. UFO is Read-Only.
Address 34
INT/TRAP Control Register (ITC, I/O Address 34H).
This register is used in handling TRAP interrupts and to
enable or disable Maskable Interrupt Level 0 and the INT1
and INT2 pins.
ITE2, 1, 0: Interrupt Enable 2, 1, 0 (bits 2-0). ITE2 and
ITE1 enable and disable the external interrupt inputs /INT2
and /INT1, respectively. ITE0 enables and disables inter-
rupts from the on-chip ESCC, CTCs and Bidirectional Cen-
tronics controller as well as the external interrupt input
/INT0. A 1 in a bit enables the corresponding interrupt level
while a 0 disables it. A Reset sets ITE0 to 1 and clears
ITE1 and ITE2 to 0.
4
1
7
6
2
0
5
3
Bit
TRAP
R/W
UFO
R
ITE2 ITE1
ITE0
––
––
––
R/W R/W R/W
TRAP (bit 7). This bit is set to 1 when an undefined Op-
code is fetched. TRAP can be reset under program control
by writing it with a 0, however, it cannot be written with 1
under program control. TRAP is reset to 0 during RESET.
TRAP Interrupt. The Z80180/Z8S180/Z8L180 generates
a non-maskable (not affected by the state of IEF1) TRAP
interrupt when an undefined Opcode fetch occurs. This
feature can be used to increase software reliability, imple-
ment an “extended” instruction set, or both. TRAP may oc-
cur during Opcode fetch cycles and also if an undefined
UFO: Undefined Fetch Object (bit 6). When a TRAP in-
terrupt occurs, the contents of UFO allow determination of
DS971800401
P R E L I M I N A R Y
1-59
ZILOG [ ZILOG, INC. ]
