Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
Table 12 shows all DMA transfer mode combinations of
DM0, DM1, SM0, and SM1. Since I/O to/from I/O transfers
are not implemented, 12 combinations are available.
Table 12. Transfer Mode Combinations
1
Address
DM1 DM0 SM1 SM0
Transfer Mode
Increment/Decrement
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
Memory→Memory
Memory→Memory
Memory*→Memory
I/O→Memory
SAR0+1, DAR0+1
SAR0–1, DAR0+1
SAR0 fixed, DAR0+1
SAR0 fixed, DAR0+1
SAR0+1, DAR0–1
SAR0–1, DAR0–1
Memory→Memory
Memory→Memory
Memory*→Memory
I/O→Memory
SAR0 fixed, DAR0–1
SAR0 fixed, DAR0–1
SAR0+1, DAR0 fixed
SAR0–1, DAR0 fixed
Memory→Memory*
Memory→Memory*
Reserved
Reserved
Memory→I/O
SAR0+1, DAR0 fixed
SAR0–1, DAR0 fixed
Memory I/O
Reserved
Reserved
Note: * Includes memory mapped I/O.
MMOD: Memory Mode Channel 0 (bit). When channel 0
is configured for memory to/from memory transfers there is
no Request Handshake signal to control the transfer tim-
ing. Instead, two automatic transfer timing modes are se-
lectable: burst (MMOD = 1) and cycle steal (MMOD = 0).
For burst memory to/from memory transfers, the DMAC
takes control of the bus continuously until the DMA transfer
completes (as shown by the byte count register = 0). In cy-
cle steal mode, the CPU is given a cycle for each DMA
byte transfer cycle until the transfer is completed.
For channel 0 DMA with I/O source or destination, the se-
lected Request signal times the transfer and thus MMOD
is ignored. MMOD is cleared to 0 during RESET.
DS971800401
P R E L I M I N A R Y
1-57
ZILOG [ ZILOG, INC. ]
