Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
DMA MODE REGISTER (DMODE).
DMODE is used to set the addressing and transfer mode
for channel 0.
Mnemonic DMODE
Address 31H
4
Bit
7
6
5
3
2
1
0
DM1
R/W
DM0
R/W
SM0
R/W
SM1
R/W
MMOD
R/W
Figure 73. DMA Mode Register (DMODE: I/O Address = 31H)
DM1, DM0: Destination Mode Channel 0 (bits 5,4) spec-
ifies whether the destination for channel 0 transfers is
memory or I/O, and whether the address should be incre-
mented or decremented for each byte transferred. DM1
and DM0 are cleared to 0 during RESET.
SM1, SM0: Source Mode Channel 0 (bits 3, 2) specifies
whether the source for channel 0 transfers is memory or
I/O, and whether the address should be incremented or
decremented for each byte transferred.
Table 11. Channel 0 Source
Table 10. Channel 0 Destination
Memory
Memory
SM1 SM0 Memory I/O Increment/Decrement
DM1 DM0 Memory I/O Increment/Decrement
0
0
1
1
0
1
0
1
Memory
Memory
Memory
I/O
+1
–1
0
0
1
1
0
1
0
1
Memory
Memory
Memory
I/O
+1
–1
fixed
fixed
fixed
fixed
1-56
P R E L I M I N A R Y
DS971800401
ZILOG [ ZILOG, INC. ]
