Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
Restart
from 0000H
1
Opcode
Fetch Cycle
Memory
Read Cycle
3nd Opcode
Fetch Cycle
PC Stacking
T
T
T
T
T
T
T
T
T
2
T
T
i
T
T
T
T
T
T
T
T
T
i
3
1
2
3
1
2
3
1
i
1
2
3
1
2
TP
3
i
φ
0000H
A -A (A )
PC
IX + d, IY + d
SP-1
PC-1
SP-2
PC-1
0
18
19
H
L
D -D
0
7
Undefined
Opcode
M1
MREQ
RD
WR
rd
Figure 77. TRAP Timing-3 Opcode Undefined
REFRESH CONTROL REGISTER
Mnemonic RCR
REFE: Refresh Enable (bit 7). REFE = disables the re-
fresh controller while REFE = 1 enables refresh cycle in-
sertion. REFE is set to 1 during RESET.
Address 36
REFW: Refresh Wait (bit 6). REFW = 0 causes the re-
fresh cycle to be two clocks in duration. REFW = 1 causes
the refresh cycle to be three clocks in duration by adding a
refresh wait cycle (TRW). REFW is set to 1 during RESET.
0
7
6
5
4
3
2
1
-
--
-- --
-- --
--
--
--
CYC1, 0: Cycle Interval (bit 1,0). CYC1 and CYC0 spec-
ify the interval (in clock cycles) between refresh cycles. In
the case of dynamic RAMs requiring 128 refresh cycles ev-
ery 2 ms (0r 256 cycles in every 4 ms), the required refresh
interval is less than or equal to 15.625 µs. Thus, the under-
lined values indicate the best refresh interval depending
on CPU clock frequency. CYC0 and CYC1 are cleared to
0 during RESET (see Table 14).
REFE
REFW
Cyc0
Cyc1
Reserved
Figure 78. Refresh Control Register
(RCA: I/O Address = 36H)
The RCR specifies the interval and length of refresh cy-
cles, while enabling or disabling the refresh function.
DS971800401
P R E L I M I N A R Y
1-61
ZILOG [ ZILOG, INC. ]
