Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
MMU BANK BASE REGISTER (BBR).
Mnemonic BBR
BBR specifies the base address (on 4 KB boundaries)
used to generate a 19-bit physical address for Bank Area
accesses. All bits of BBR are reset to 0 during RESET.
1
Address 39
5
4
3
2
1
0
7
6
Bit
BB7
R/W
BB6
R/W
BB5
R/W
BB4
R/W
BB3
R/W
BB0
R/W
BB2
R/W
BB1
R/W
Figure 80. MMU Bank Base Register (BBR: I/O Address = 39H)
MMU COMMON/BANK AREA REGISTER (CBAR).
Mnemonic CBAR
CBAR
specifies
boundaries
within
the
Z80180/Z8S180/Z8L180 64 KB logical address space for
up to three areas; Common Area), Bank Area and Com-
mon Area 1.
Address 3A
MMU Common/Bank Area Register (CBAR: I/O Address = 3 AH)
5
4
3
2
1
0
7
6
Bit
CA3
R/W
CA2
R/W
CA1
R/W
CA0
R/W
BA3
R/W
BA0
R/W
BA2
R/W
BA1
R/W
Figure 81. MMU Common/Bank Area Register (CBAR: I/O Address = 3 AH
CA3-CA0:CA (bits 7-4). CA specifies the start (Low) ad-
dress (on 4 KB boundaries) for the Common Area 1. This
also determines the last address of the Bank Area. All bits
of CA are set to 1 during RESET.
BA-BA0 (bits 3-0). BA specifies the start (Low) address
(on 4 KB boundaries) for the Bank Area. This also deter-
mines the last address of the Common Area 0. All bits of
BA are set to 1 during RESET.
DS971800401
P R E L I M I N A R Y
1-63
ZILOG [ ZILOG, INC. ]
