Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
DMA/WAIT CONTROL REGISTER (DCNTL)
DCNTL controls the insertion of wait states into DMAC
(and CPU) accesses of memory or I/O. Also, it defines the
Request signal for each channel as level or edge sense.
DCNTL also sets the DMA transfer mode for channel 1,
which is limited to memory to/from I/O transfers.
Bit
7
6
5
4
3
2
1
0
MWI1
R/W
MWI0
R/W
IWI0
R/W
DMS0
R/W
DIM0
R/W
IWI1
R/W
DMS1
R/W
DIM1
R/W
Figure 74. DMA/WAIT Control Register (DCNTL: I/O Address = 32H)
MWI1, MWI0: Memory Wait Insertion (bits 7-6). Speci-
DMS1, DMS0: DMA Request Sense (bits 3-2). DMS1
and DMS0 specify the DMA request sense for channel 0
and channel 1 respectively. When reset to 0, the input is
level sense. When set to 1, the input is edge sense. DMS1
and DMS0 are cleared to 0 during RESET.
fies the number of wait states introduced into CPU or
DMAC memory access cycles. MWI1 and MWI0 are set to
1 during RESET.
MWI1
MWI0
Wait State
DMSi
Sense
0
0
1
1
0
1
0
1
0
1
2
3
1
0
Edge Sense
Level Sense
Typically, for an input/source device, the associated DMS
bit should be programmed as 0 for level sense because
the device has a relatively long time to update its Request
signal after the DMA channel reads data from it in the first
of the two machine cycles involved in transferring a byte.
IWI1, IWI0: I/O Wait Insertion (bits 5-4). Specifies the
number of wait states introduced into CPU or DMAC I/O
access cycles. IWI1 and IWI0 are set to 1 during RESET.
See the section on Wait-State Generation for details.
An output/destination device has much less time to update
its Request signal, after the DMA channel starts a write op-
eration to it, as the second machine cycle of the two cycles
involved in transferring a byte. With zero-wait state I/O cy-
cles, which apply only to the ASCIs, it is impossible for a
device to update its Request signal in time, and edge sens-
ing must be used.
IWI1
IWI0
Wait State
0
0
1
1
0
1
0
1
0
2
3
4
1-58
P R E L I M I N A R Y
DS971800401
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