Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
ø
32
31
/INTi
33
/NMI
/MI *1
/IORQ *1
Date IN *1
30
14
10
28
29
15
16
39
/MREQ *2
/RFSH *2
42
41
40
35
34
35
34
/BUSREQ
36
38
37
/BUSACk
38
ADDRESS
DATA
/MREQ /RD
/WR, /IORQ
*3
43
44
/HALT
Notes:
1. During /INT acknowledge cycle.
0
2. During refresh cycle.
3. Output buffer is off at this point.
Figure 21. CPU Timing
(/INT Acknowledge Cycle, Refresh Cycle, BUS RELEASE Mode,
0
HALT Mode, SLEEP Mode, SYSTEM STOP Mode)
1-30
P R E L I M I N A R Y
DS971800401