Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
Z80180-20
Z80180-33
No.
38.
Symbol Item
Min.
Max.
10
–
Min.
Max.
25
–
Unit
t
t
t
t
t
t
t
t
t
t
t
t
t
Ø Rise to Bus Floating Delay Time
/MREQ Pulse Width (HIGH)
/MREQ Pulse Width (LOW)
Ø Rise to /RFSH Fall Delay
Ø Rise to /RFSH Rise Delay
Ø Rise to /HALT Fall Delay
Ø Rise to /HALT Rise Delay
/DREQi Set-up Time to Ø Rise
/DREQi Hold Time from Ø Rise
Ø Fall to /TENDi Fall Delay
Ø Fall to /TENDI Rise Delay
Ø Rise to E Rise Delay
–
45
45
–
–
25
25
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
BZD
39.
40.
41.
42.
43.
44.
45.
46.
47.
48.
49.
50.
51.
52.
53.
54.
55.
56.
MEWH
MEWL
RFD1
RFD2
HAD1
HAD2
DRQS
DRQH
TED1
TED2
ED1
–
–
15
15
15
15
–
15
15
15
15
–
–
–
–
–
–
–
20
15
–
20
15
–
–
–
15
15
15
15
–
15
15
15
15
–
–
–
–
–
Ø Fall or Rise to E Fall Delay
E Pulse Width (HIGH)
–
–
ED2
P
P
45
70
–
20
20
–
WEH
E Pulse Width (LOW)
–
–
WEL
t
t
t
t
Enable Rise Time
10
10
50
2
10
10
50
2
Er
Enable Fall Time
–
–
Ef
Ø Fall to Timer Output Delay
–
–
TOD
STDI
CSI/O Transmit Data Delay Time (Internal Clock
Operation)
–
–
57.
58.
59.
60.
61.
t
t
t
t
t
CSI/O Transmit Data Delay Time (External Clock
Operation)
–
1
1
1
1
7.5tcyc
+75
–
1
1
1
1
7.5tcyc
+60
ns
STDE
SRSI
CSI/O Receive Data Set-up Time (Internal Clock
Operation)
–
–
–
–
–
–
–
–
tcyc
tcyc
tcyc
tcyc
CSI/O Receive Data Hold Time (Internal Clock
Operation)
SRHI
SRSE
SRHE
CSI/O Receive Data Set-up Time (External Clock
Operation)
CSI/O Receive Data Hold Time (External Clock
Operation)
62.
63.
64.
65.
66.
67.
68.
69.
70.
t
t
t
t
t
t
t
t
t
/RESET Set-up Time to Ø Fall
/RESET Hold Time from Ø Fall
Oscillator Stabilization Time
External Clock Rise Time (EXTAL)
External Clock Fall Time (EXTAL)
/RESET Rise Time
25
15
–
–
25
15
–
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
RES
REH
OSC
EXr
EXf
Rr
–
20
10
10
50
50
50
50
20
5
–
–
–
–
5
–
–
50
50
50
50
/RESET Fall Time
–
–
Rf
Input Rise Time (except EXTAL, /RESET)
Input Fall Time (except EXTAL, /RESET)
–
–
Ir
–
–
If
1-28
P R E L I M I N A R Y
DS971800401
ZILOG [ ZILOG, INC. ]
