Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
AC CHARACTERISTICS
(V = 5V ±10% or V = 3.3V ±10% over specified temperature range, unless otherwise noted, 33
CC
CC
MHZ characteristics apply only to 5V operation.)
1
Z80180-20
Z80180-33
No.
1.
Symbol Item
Min.
Max.
2000
–
Min.
Max.
2000
–
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
t
t
t
t
t
t
t
Clock Cycle Time
50
15
15
–
33
10
10
–
cyc
2.
3.
4.
5.
6.
7.
8.
9.
Clock “H” Pulse Width
CHW
CLW
cf
Clock “L” Pulse Width
–
–
Clock Fall Time
10
10
15
–
5
Clock Rise Time
–
–
5
cr
ØRise to Address Valid Delay
Address Valid to /MREQ Fall or /IORQ Fall)
Ø Fall to /MREQ Fall Delay
Ø Fall to /RD Fall Delay /IOC = 1
Ø Rise to /RD Rise Delay /IOC = 0
Ø Rise to /M1 Fall Delay
–
–
15
–
AD
20
–
5
AS
15
15
15
15
20
–
15
15
15
15
–
MED1
RDD1
–
–
–
–
10.
11.
t
t
–
–
ns
ns
M1D1
Address Hold Time from
–
5
AH
(/MREQ, /IOREQ, /RD, /WR)
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
25.
26.
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
–
–
15
15
15
–
–
–
15
15
15*
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Ø Fall to /MREQ Rise Delay
Ø Fall to /RD Rise Delay
Ø Rise to /M1 Rise Delay
Data Read Set-up Time
MED2
RDD2
M1D2
DRS
–
–
15
0
15
0
Data Read Hold Time
–
–
DRH
–
15
15
–
–
15
15
–
Ø Fall to ST Fall Delay
STD1
STD2
WS
–
–
Ø Fall to ST Rise Delay
/WAIT Set-up Time to Ø Fall
/WAIT Hold Time from Ø Fall
Ø Rise to Data Float Delay
Ø Rise to /WR Fall Delay
Ø Fall to Write Data Delay Time
Write Data Set-up Time to /WR Fall
15
5
15
5
–
–
WH
–
10
15
20
–
–
10
15
20
–
WDZ
WRD1
WDD
WDS
WRD2
WRP
–
–
–
–
10
–
0
15
–
–
15
–
Ø Fall to /WR Rise Delay
/WR Pulse Width
70
40
26a.
27.
/WR Pulse Width (I/O Write Cycle)
Write Data Hold Time from (/WR Rise)
Ø Fall to /IORQ Fall Delay /IOC = 1
Ø Rise to /IORQ Fall Delay /IOC = 1
Ø Fall to /IORQ Rise Delay
/M1 Fall to /IORQ Fall Delay
/INT Set-up Time to Ø Fall
120
5
–
–
70
5
–
–
t
t
WDH
28.
–
–
15
15
15
–
–
–
15
15
15
–
ns
IOD1
29.
30.
31.
32.
33.
34.
35.
36.
37.
t
t
t
t
t
t
t
t
t
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
IOD2
IOD3
INTS
INTS
NMIW
BRS
120
15
10
35
10
10
–
70
15
10
25
10
10
–
–
–
/INT Hold Time from Ø Fall
/NMI Pulse Width
–
–
–
–
/BUSREQ Set-up Time to Ø Fall
/BUSREQ Hold Time from Ø Fall
–
–
–
BRH
15
15
15
15
Ø Rise to /BUSACK Fall Delay
Ø Fall to /BUSACK Rise Delay
BAD1
BAD2
–
–
DS971800401
P R E L I M I N A R Y
1-27
ZILOG [ ZILOG, INC. ]
