Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
T1
T2
TW
TW
T3
ø
49
50
E
(Memory Read//Write)
49
50
E
(I/O Read)
49
50
E
15
16
(I/O Write)
D0 - D7
Figure 24. E Clock Timing
(Memory Read/Write Cycle, I/O Read/Write Cycle)
ø
E
49
50
BUS RELEASE mode
SLEEP mode
SYSTEM STOP mode
Figure 25. E Clock Timing
(BUS RELEASE Mode, SLEEP Mode, SYSTEM STOP Mode)
T2
TW
T3
T1
T2
50
54
49
53
52
E
Example
I/O read
→ Opcode fetch
50
49
51
53
54
Figure 26. E Clock Timing
(Minimum timing example of P and P
)
WEH
WEL
1-32
P R E L I M I N A R Y
DS971800401