Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
I/O Write Cycle
I/O Read Cycle
1
T
T
T
T
T
T
T
T
3
1
2
w
3
1
2
w
φ
ADDRESS
28
9
29
28
22
29
25
IROQ
RD
13
WR
I/O Read Cycle
CPU Timing (IOC=0)
I/O Write Cycle
Figure 22. CPU Timing (/IOC = 0)
(I/O Read Cycle, I/O Write Cycle)
CPU or DMA Read/Write Cycle (Only DMA Write Cycle for /TENDi)
T
T
T
T
T
1
1
2
W
3
ø
*1
46
45
/DREQi
(at level sense)
*2
45 46
/DREQi
(at level sense)
*4
18
47
48
/TENDi
ST
*3
17
1. t
and t
and t
are specified for the rising edge of clock followed by T .
DRQS
DHQH
3
*2. t
are specified for the rising edge of clock.
DRQS
DHQH
*3. DMA cycle starts.
*4. CPU cycle starts
Figure 23. DMA Control Signals
P R E L I M I N A R Y
DS971800401
1-31
ZILOG [ ZILOG, INC. ]
