Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
Z80180-6
Z80180-8
Z80180-10
No. Symbol Item
Min.
Max.
–
Min.
Max.
–
Min.
Max.
–
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
40.
41.
42.
43.
44.
45.
46.
47.
48.
49.
50.
51.
52.
53.
54.
55.
56.
t
t
t
t
t
t
t
t
t
t
t
/MREQ Pulse Width (LOW)
Ø Rise to /RFSH Fall Delay
Ø Rise to /RFSH Rise Delay
Ø Rise to /HALT Fall Delay
Ø Rise to /HALT Rise Delay
/DREQi Set-up Time to Ø Rise
/DREQi Hold Time from Ø Rise
Ø Fall to /TENDi Fall Delay
Ø Fall to /TENDI Rise Delay
Ø Rise to E Rise Delay
125
–
100
–
80
–
MEWL
RFD1
RFD2
HAD1
HAD2
DRQS
DRQH
TED1
TED2
ED1
90
90
90
90
–
80
80
80
80
–
60
60
50
50
–
–
–
–
–
–
–
–
–
–
40
40
–
40
40
–
30
30
–
–
–
–
70
70
95
95
–
60
60
70
70
–
50
50
60
60
–
–
–
–
–
–
–
Ø Fall or Rise to E Fall Delay
E Pulse Width (HIGH)
–
–
–
ED2
P
P
75
180
–
65
130
–
55
110
–
WEH
WEL
E Pulse Width (LOW)
–
–
–
t
t
t
t
Enable Rise Time
20
20
300
200
20
20
200
200
20
20
150
150
Er
Enable Fall Time
–
–
–
Ef
Ø Fall to Timer Output Delay
–
–
–
TOD
STDI
CSI/O Transmit Data Delay Time (Internal
Clock Operation)
–
–
–
57.
58.
59.
60.
61.
t
t
t
t
t
CSI/O Transmit Data Delay Time (External
Clock Operation)
–
1
1
1
1
7.5tcyc
+300
–
1
1
1
1
7.5tcyc
+200
–
1
1
1
1
7.5tcyc
+150
ns
STDE
SRSI
CSI/O Receive Data Set-up Time (Internal
Clock Operation)
–
–
–
–
–
–
–
–
–
–
–
–
tcyc
tcyc
tcyc
tcyc
CSI/O Receive Data Hold Time (Internal
Clock Operation)
SRHI
SRSE
SRHE
CSI/O Receive Data Set-up Time (External
Clock Operation)
CSI/O Receive Data Hold Time (External
Clock Operation)
62.
63.
64.
65.
66.
67.
68.
69.
70.
t
t
t
t
t
t
t
t
t
/RESET Set-up Time to Ø Fall
/RESET Hold Time from Ø Fall
Oscillator Stabilization Time
External Clock Rise Time (EXTAL)
External Clock Fall Time (EXTAL)
/RESET Rise Time
120
80
–
–
–
100
70
–
–
–
80
50
–
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
RES
REH
OSC
EXr
EXf
Rr
20
25
25
50
50
100
100
20
25
25
50
50
100
100
TBD
25
–
–
–
–
–
–
25
–
–
–
50
/RESET Fall Time
–
–
–
50
Rf
Input Rise Time (except EXTAL, /RESET)
Input Fall Time (except EXTAL, /RESET)
–
–
–
100
100
Ir
–
–
–
If
1-26
P R E L I M I N A R Y
DS971800401