Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
TIMING DIAGRAMS
Opcode fetch Cycle
I/O Write Cycle *2
I/O Read Cycle *2
T
2
T
T
T
T
T
T
T
T
1
1
2
W
1
2
W
3
1
3
3
4
5
ø
1
6
ADDRESS
20
20
19
19
/WAIT
/MREQ
/IORQ
/RD
7
11
12
13
7
8
29
13
11
11
28
9
11
9
22
25
/WR
/M1
ST
14
18
10
17
15
16
15
21
27
16
Data IN
24
23
Data OUT
*1
62
63
62
63
/RESET
68
67
67
68
Notes:
*1. Output buffer is off at this point.
*2. Memory Read/Write Cycle timing are the same as I/O Read/Write Cycle except
there are no automatic wait states (T ), and /MREQ is active instead of /IORQ.
W
Figure 20. CPU Timing
(Opcode Fetch Cycle, Memory Read Cycle,
Memory Write Cycle, I/O Write Cycle, I/O Read Cycle)
DS971800401
P R E L I M I N A R Y
1-29
ZILOG [ ZILOG, INC. ]
