Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
AC CHARACTERISTICS
V
= 5V + 10%, V = 0V, T - 0 to +70° C, unless otherwise noted.
cc
ss A
1
Z80180-6
Z80180-8
Z80180-10
No. Symbol Item
Min.
Max.
2000
–
Min.
125
50
50
–
Max.
2000
–
Min.
Max.
2000
–
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
1.
2.
3.
4.
5.
6.
7.
8.
9.
t
t
t
t
t
t
t
t
t
Clock Cycle Time
162
65
65
–
100
40
40
–
cyc
Clock “H” Pulse Width
CHW
CLW
cf
Clock “L” Pulse Width
–
–
–
Clock Fall Time
15
15
90
–
15
15
80
–
10
10
70
–
Clock Rise Time
–
–
–
cr
ØRise to Address Valid Delay
Address Valid to /MREQ Fall or /IORQ Fall)
Ø Fall to /MREQ Fall Delay
Ø Fall to /RD Fall Delay /IOC = 1
Ø Rise to /RD Rise Delay /IOC = 0
Ø Rise to /M1 Fall Delay
–
–
–
AD
30
–
20
–
10
–
AS
60
60
65
80
–
50
50
60
70
–
50
50
55
60
–
MED1
RDD1
–
–
–
–
–
–
10.
11.
t
t
–
–
–
ns
ns
M1D1
AH
Address Hold Time from
35
20
10
(/MREQ, /IOREQ, /RD, /WR)
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
25.
26.
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
–
–
60
60
80
–
–
–
50
50
70*
–
–
–
50
50
60
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Ø Fall to /MREQ Rise Delay
Ø Fall to /RD Rise Delay
Ø Rise to /M1 Rise Delay
Data Read Set-up Time
MED2
RDD2
M1D2
DRS
–
–
–
40
0
30
0
25
0
Data Read Hold Time
–
–
–
DRH
–
90
90
–
–
70
70
–
–
60
60
–
Ø Fall to ST Fall Delay
STD1
STD2
WS
–
–
–
Ø Fall to ST Rise Delay
/WAIT Set-up Time to Ø Fall
/WAIT Hold Time from Ø Fall
Ø Rise to Data Float Delay
Ø Rise to /WR Fall Delay
Ø Fall to Write Data Delay Time
Write Data Set-up Time to /WR Fall
40
40
–
40
40
–
30
30
–
–
–
–
WH
95
65
90
–
70
60
80
–
60
50
60
–
WDZ
WRD1
WDD
WDS
WRD2
WRP
–
–
–
–
–
–
40
–
20
–
15
–
80
–
60
–
50
–
Ø Fall to /WR Rise Delay
/WR Pulse Width
170
130
110
26a.
27.
/WR Pulse Width (I/O Write Cycle)
Write Data Hold Time from (/WR Rise)
Ø Fall to /IORQ Fall Delay /IOC = 1
Ø Rise to /IORQ Fall Delay /IOC = 1
Ø Fall to /IORQ Rise Delay
/M1 Fall to /IORQ Fall Delay
/INT Set-up Time to Ø Fall
332
40
–
–
255
15
–
–
210
10
–
–
t
t
WDH
IOD1
28.
–
–
60
65
60
–
–
–
50
60
50
–
–
–
50
55
50
–
ns
29.
30.
31.
32.
33.
34.
35.
36.
37.
38.
39.
t
t
t
t
t
t
t
t
t
t
t
–
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
IOD2
IOD3
INTS
INTS
NMIW
BRS
340
40
40
120
40
40
–
250
40
40
100
40
40
–
200
30
30
80
30
30
–
–
–
–
/INT Hold Time from Ø Fall
/NMI Pulse Width
–
–
–
–
–
–
/BUSREQ Set-up Time to Ø Fall
/BUSREQ Hold Time from Ø Fall
–
–
–
–
BRH
95
90
125
–
70
70
90
–
60
60
80
–
Ø Rise to /BUSACK Fall Delay
Ø Fall to /BUSACK Rise Delay
Ø Rise to Bus Floating Delay Time
/MREQ Pulse Width (HIGH)
BAD1
BAD2
BZD
–
–
–
–
–
–
110
90
70
MEWH
DS971800401
P R E L I M I N A R Y
1-25
ZILOG [ ZILOG, INC. ]
