<ꢀ5ꢁꢀꢂꢃ<ꢀ.ꢁꢀꢂ
'PJCPEGFꢄ<ꢁꢀꢂꢄ/KETQRTQEGUUQT
ZiLOG
&/#ꢄ/1&'ꢄ4')+56'4
The DMA Mode Register (&/1&') is used to set the ad-
dressing and transfer mode for channel 0.
&/#ꢄ/QFGꢄ4GIKUVGT
/PGOQPKEꢄ&/1&'
#FFTGUUꢄꢋꢁ*
ꢎ
ꢄ
$KV
ꢊ
ꢁ
ꢏ
ꢍ
ꢂ
ꢀ
&/ꢄ
&/ꢀ
4ꢌ9
5/ꢄ
4ꢌ9
5/ꢀ //1&
4ꢌ9
4ꢌ9
4ꢌ9
(KIWTG ꢐꢇꢆ &/#ꢄ/QFGꢄ4GIKUVGTꢄꢌ&/1&'ꢅꢄ+ꢃ1ꢄ#FFTGUUꢄꢒꢄꢋꢁ*ꢍ
&/ꢁꢎꢄ&/ꢂꢅꢄ&GUVKPCVKQPꢄ/QFGꢄ%JCPPGNꢄꢂꢄꢌ$KVUꢄꢑꢎꢉꢍꢆꢄThis
5/ꢁꢎꢄ5/ꢂꢅꢄ5QWTEGꢄ/QFGꢄ%JCPPGNꢄꢂꢄꢌ$KVUꢄꢋꢎꢄꢇꢍꢄꢆꢄThis
mode specifies whether the source for channel 0 transfers
is memory or I/O, and whether the address should be incre-
mented or decremented for each byte transferred.
mode specifies whetherthe destination for channel 0 transfers
is memory or I/O, and whether the address should be incre-
mented or decremented for each byte transferred. &/ꢄ and
&/ꢀ are cleared toꢅ0during 4'5'6
.
6CDNG ꢁꢑꢆ %JCPPGNꢄꢂꢄ5QWTEG
/GOQT[ꢄ
6CDNG ꢁꢉꢆ %JCPPGNꢄꢂꢄ&GUVKPCVKQP
/GOQT[ꢄ
5/ꢁ 5/ꢂ /GOQT[ꢄ+ꢃ1
+PETGOGPVꢃ&GETGOGPV
&/ꢁ &/ꢂ /GOQT[ꢄ+ꢃ1
+PETGOGPVꢃ&GETGOGPV
ꢀ
ꢀ
ꢄ
ꢄ
ꢀ
ꢄ
ꢀ
ꢄ
/GOQT[
/GOQT[
/GOQT[
+ꢌ1
ꢔꢄ
ꢄ
HKZGF
HKZGF
ꢀ
ꢀ
ꢄ
ꢄ
ꢀ
ꢄ
ꢀ
ꢄ
/GOQT[
/GOQT[
/GOQT[
+ꢌ1
ꢔꢄ
ꢄ
HKZGF
HKZGF
&5ꢀꢀꢁꢀꢀꢂꢃ</2ꢀꢂꢀꢀ
2ꢅ4ꢅ'ꢅ.ꢅ+ꢅ/ꢅ+ꢅ0ꢅ#ꢅ4ꢅ;
ꢏꢋ
ZILOG [ ZILOG, INC. ]
