<ꢀ5ꢁꢀꢂꢃ<ꢀ.ꢁꢀꢂ
'PJCPEGFꢄ<ꢁꢀꢂꢄ/KETQRTQEGUUQT
ZiLOG
Table 16 indicates all DMA transfer mode combinations of
&/ꢀ, &/ꢄ, 5/ꢀ, and 5/ꢄ. Because I/O to/from I/O trans-
fers are not implemented, 12 combinations are available.
6CDNG ꢁꢈꢆ 6TCPUHGTꢄ/QFGꢄ%QODKPCVKQPU
5/ꢂ 6TCPUHGTꢄ/QFG #FFTGUUꢄ+PETGOGPVꢃ&GETGOGPV
&/ꢁ
&/ꢂ
5/ꢁ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢄ
ꢄ
ꢄ
ꢄ
ꢄ
ꢄ
ꢄ
ꢄ
ꢀ
ꢀ
ꢀ
ꢀ
ꢄ
ꢄ
ꢄ
ꢄ
ꢀ
ꢀ
ꢀ
ꢀ
ꢄ
ꢄ
ꢄ
ꢄ
ꢀ
ꢀ
ꢄ
ꢄ
ꢀ
ꢀ
ꢄ
ꢄ
ꢀ
ꢀ
ꢄ
ꢄ
ꢀ
ꢀ
ꢄ
ꢄ
ꢀ
ꢄ
ꢀ
ꢄ
ꢀ
ꢄ
ꢀ
ꢄ
ꢀ
ꢄ
ꢀ
ꢄ
ꢀ
ꢄ
ꢀ
ꢄ
/GOQT[→/GOQT[
/GOQT[→/GOQT[
/GOQT[ꢕ→/GOQT[
+ꢌ1→/GOQT[
/GOQT[→/GOQT[
/GOQT[→/GOQT[
/GOQT[ꢕ→/GOQT[
+ꢌ1→/GOQT[
/GOQT[→/GOQT[ꢕ
/GOQT[→/GOQT[ꢕ
4GUGTXGF
4GUGTXGF
/GOQT[→+ꢌ1
5#4ꢀꢔꢄꢇꢅꢀꢔꢄ
5#4ꢀ ꢄꢇꢅꢀꢔꢄ
5#4ꢀꢅHKZGFꢇꢅꢀꢔꢄ
5#4ꢀꢅHKZGFꢇꢅꢀꢔꢄ
5#4ꢀꢔꢄꢇꢅꢀ ꢄ
5#4ꢀ ꢄꢇꢅꢀ ꢄ
5#4ꢀꢅHKZGFꢇꢅꢀ ꢄ
5#4ꢀꢅHKZGFꢇꢅꢀ ꢄ
5#4ꢀꢔꢄꢇꢅꢀꢅHKZGF
5#4ꢀ ꢄꢇꢅꢀꢅHKZGF
5#4ꢀꢔꢄꢇꢅꢀꢅHKZGF
5#4ꢀ ꢄꢇꢅꢀꢅHKZGF
/GOQT[→+ꢌ1
4GUGTXGF
4GUGTXGF
0QVGꢅꢄ* Includes memory mapped I/O.
//1&ꢅꢄ/GOQT[ꢄ/QFGꢄ%JCPPGNꢄꢂꢄꢌ$KVꢄꢁꢍꢆꢄWhen chan-
nel 0 is configured for memory to/from memory transfers
there is no Request Handshake signal to control the transfer
timing. Instead, twoautomatictransfertimingmodesarese-
lectable: burst (//1&ꢅꢐꢅꢄ) and cycle steal (//1&ꢅꢐꢅꢀ).
For burst memory to/from memory transfers, the DMAC
takescontrolofthebuscontinuouslyuntiltheDMAtransfer
completes (as indicated by the byte count register = ꢀ). In
cyclestealmode, theCPUisprovidedacycleforeachDMA
byte transfer cycle until the transfer is completed.
For channel 0 DMA with I/O source or destination, the se-
lected Request signal times the transfer ignoring //1&.
//1& is cleared toꢅ0during 4'5'6.
ꢁꢀ
2ꢅ4ꢅ'ꢅ.ꢅ+ꢅ/ꢅ+ꢅ0ꢅ#ꢅ4ꢅ;
&5ꢀꢀꢁꢀꢀꢂꢃ</2ꢀꢂꢀꢀ
ZILOG [ ZILOG, INC. ]
