<ꢀ5ꢁꢀꢂꢃ<ꢀ.ꢁꢀꢂ
'PJCPEGFꢄ<ꢁꢀꢂꢄ/KETQRTQEGUUQT
ZiLOG
&/#ꢄ56#675ꢄ4')+56'4
The DMA Status Register (&56#6) is used to enable and
&56#6 also indicates DMA transfer status, Completed or
disable DMA transfer and DMA termination interrupts.
In Progress.
&/#ꢄ5VCVWUꢄ4GIKUVGT
/PGOQPKEꢄ&56#6
#FFTGUUꢄꢋꢂ*
ꢎ
ꢄ
ꢏ
ꢍ
$KV
ꢊ
ꢁ
ꢂ
ꢀ
&'ꢄ
4ꢌ9
&'ꢀ
4ꢌ9
&+'ꢀ
4ꢌ9
&/'
4
&9'ꢄ &9'ꢀ &+'ꢄ
4ꢌ9
9
9
(KIWTG ꢐꢁꢆ &/#ꢄ5VCVWUꢄ4GIKUVGTꢄꢌ&56#6ꢅꢄ+ꢃ1ꢄ#FFTGUUꢄꢒꢄꢋꢂ*ꢍ
&'ꢁꢅꢄ&/#ꢄ'PCDNGꢄ%JCPPGNꢄꢁꢄꢌ$KVꢄꢐꢍꢆꢄWhen &'ꢄꢅꢐ 1
&+'ꢁꢅꢄ&/#ꢄ+PVGTTWRVꢄ'PCDNGꢄ%JCPPGNꢄꢁꢄꢌ$KVꢄꢋꢍꢆꢄWhen
&+'ꢀ is set to 1, the termination channel 1 DMA transfer
(indicated when &'ꢄꢅꢐꢅ0) causes a CPU interrupt request
to be generated. When &+'ꢀꢅꢐꢅ0, the channel 0 DMA ter-
mination interrupt is disabled. &+'ꢀ is cleared toꢅ0during
4'5'6.
and &/'ꢅꢐ 1, channel 1 DMA is enabled. When a DMA
transfer terminates ($%4ꢄꢅꢐꢅꢀ), &'ꢄ is reset toꢅ0by the
DMAC. When &'ꢄꢅꢐꢅ0and the DMA interrupt is enabled
(&+'ꢄ ꢐ 1), a DMA interrupt request is made to the CPU.
To perform a software 94+6' to &'ꢄ, &9'ꢄ should be
written withꢅaꢅ0during the same register 94+6' access.
Writing &'ꢄ toꢅ0disables channel 1 DMA, but DMA is re-
startable. Writing &'ꢄ to 1 enables channel 1 DMA and
automatically sets DMA Main Enable (&/') to 1. &'ꢄ is
cleared toꢅ0during 4'5'6.
&+'ꢂꢅꢄ&/#ꢄ+PVGTTWRVꢄ'PCDNGꢄ%JCPPGNꢄꢂꢄꢌ$KVꢄꢇꢍꢆꢄWhen
&+'ꢀ is set to 1, the termination channel 0 of DMA transfer
(indicated when &'ꢀꢅꢐꢅꢀ) causes a CPU interrupt request
to be generated. When &+'ꢀꢅꢐꢅ0, the channel 0 DMA ter-
mination interrupt is disabled. &+'ꢀ is cleared toꢅ0during
4'5'6.
&'ꢂꢅꢄ&/#ꢄ'PCDNGꢄ%JCPPGNꢄꢂꢄꢌ$KVꢄꢈꢍꢆꢄWhen &'ꢀꢅꢐ 1
and &/'ꢅꢐ 1, channel 0 DMA is enabled. When a DMA
transfer terminates ($%4ꢀꢅꢐꢅꢀ), &'ꢀ is reset toꢅ0by the
DMAC. When &'ꢀꢅꢐꢅ0and the DMA interrupt is enabled
(&+'ꢀ ꢐ 1), a DMA interrupt request is made to the CPU.
&/'ꢅꢄ&/#ꢄ/CKPꢄ'PCDNGꢄꢌ$KVꢄꢂꢍꢆꢄA DMA operation is
only enabled when its &' bit (&'ꢀ for channelꢅ0, &'ꢄ for
channel 1) and the &/'ꢅbit is set to ꢄ.
When 0/+ occurs, &/' is reset toꢅ0, thus disabling DMA
activity during the 0/+ interrupt service routine. To restart
DMA, &' and/or &'ꢄ should be written with a 1 (even
if the contents are already ꢄ). This condition automatically
sets &/' to 1, allowing DMA operations to continue.
To perform a software 94+6' to &'ꢀ, &9'ꢀ should be
written withꢅ0duringthe same register94+6' access. Writ-
ing &'ꢀ toꢅ0disables channel 0 DMA. Writing &'ꢀ to 1
enables channel 0 DMA and automatically sets DMA Main
Enable (&/') to 1. &'ꢀ is cleared toꢅ0during 4'5'6.
0QVGꢅ &/' cannot be directly written. The bit is cleared to 0
by 0/+ or indirectly set to 1 by setting &'ꢀ and/or &'ꢄ
to 1. &/' is cleared to 0during 4'5'6.
&9'ꢁꢅꢄ&'ꢁꢄ$KVꢄ9TKVGꢄ'PCDNGꢄꢌ$KVꢄꢑꢍꢆꢄWhen performing
any software 94+6' to &'ꢄ, this bit should be written with
0during the same access. &9'ꢄ always reads as ꢄ.
&9'ꢂꢅꢄ&'ꢂꢄ$KVꢄ9TKVGꢄ'PCDNGꢄꢌ$KVꢄꢉꢍꢆꢄWhen performing
any software 94+6' to &'ꢀ, this bit should be written with
0during the same access. &9'ꢀ always reads as ꢄ.
ꢏꢆ
2ꢅ4ꢅ'ꢅ.ꢅ+ꢅ/ꢅ+ꢅ0ꢅ#ꢅ4ꢅ;
&5ꢀꢀꢁꢀꢀꢂꢃ</2ꢀꢂꢀꢀ
ZILOG [ ZILOG, INC. ]
