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DKVUꢌUGEQPFꢅꢐꢅH ꢌꢈꢂꢕꢈ6%ꢔꢂꢉꢅZꢅUCORNKPIꢅTCVGꢉ
If the 55ꢂ ꢀ bits of the %06.$ register are not ꢄꢄꢄ, and
the $4) mode bit in the #5':6 register is 1, the #5%+ di-
vides the 2*+ clock by two times the registers’ 16-bit value,
plustwo.Asaresult, theclock ispresentedtothetransmitter
and receiver for division by 1, 16, or 64, and is output on
the %-# pin.
where 6% is the 16-bit value programmed into the ASCI
Time Constant High and Low registers. If the ASCI multi-
plexed %-# pin is selected for the %-# function, it outputs
the clock before the final division by the sampling rate, as
follows:
If the 55ꢂ ꢀ bits in an ASCI %06.$ register are not 111,
and the $4) mode bit in its Extension Control Register is
1, itsnew baudrate generatordivides2*+ forserial clocking,
as follows:
H
ꢅꢐꢅH ꢌꢈꢂꢕꢈ6%ꢔꢂꢉꢉ
Find the 6% value for a particular serial bit rate as follows:
6%ꢅꢐꢅꢈH ꢌꢈꢂꢅZꢅDKVUꢌUGEQPFꢅZꢅUCORNKPIꢅTCVGꢉꢉꢅ ꢅꢂ
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ZILOG [ ZILOG, INC. ]
