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Z8S18020VSG 参数 Datasheet PDF下载

Z8S18020VSG图片预览
型号: Z8S18020VSG
PDF下载: 下载PDF文件 查看货源
内容描述: 两个链条链接的DMA通道 [Two Chain-Linked DMA Channels]
分类和应用: 微控制器和处理器外围集成电路微处理器时钟
文件页数/大小: 71 页 / 2080 K
品牌: ZILOG [ ZILOG, INC. ]
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'PJCPEGFꢄ<ꢁꢀꢂꢄ/KETQRTQEGUUQT  
ZiLOG  
6+/'4ꢄ%10641.ꢄ4')+56'4  
The Timer Control Register (6%4) monitors both channels  
(246ꢀꢇꢅ246ꢄ) 6/&4 status. It also controls the enabling  
anddisablingofdown-countingandinterrupts, andcontrols  
the output pin #ꢄꢆꢌ6  
for 246ꢄ.  
$KV  
6+(ꢀ  
4
6+'ꢄ  
4ꢌ9  
6+'ꢀ  
4ꢌ9  
61%ꢄ  
4ꢌ9  
61%ꢀ  
4ꢌ9  
6&'ꢄ  
4ꢌ9  
6&'ꢀ  
4ꢌ9  
ꢅ6+(ꢄ  
4
(KIWTG ꢉꢈꢆ 6KOGTꢄ%QPVTQNꢄ4GIKUVGTꢄꢌ6%4ꢅꢄ+ꢃ1ꢄ#FFTGUUꢄꢒꢄꢁꢂ*ꢍ  
6+(ꢁꢅꢄ6KOGTꢄ+PVGTTWRVꢄ(NCIꢄꢁꢄꢌ$KVꢄꢐꢍꢄꢆꢄWhen 6/&4ꢄ dec-  
rements to0, 6+(ꢄ is set to 1. This condition generates an  
interrupt request if enabled by 6+'ꢄꢅꢐ 1. 6+(ꢄ is reset to0  
when 6%4 is read and the higher or lower byte of 6/&4ꢄ  
is read. During 4'5'6, 6+(ꢄ is cleared to 0.  
61%ꢄ and 61%ꢀ, the #ꢄꢆꢌ6  
Low, or toggled when 6/&4ꢄ decrements to 0.  
pin can be forced High,  
6CDNG ꢁꢇꢆ 6KOGTꢄ1WVRWVꢄ%QPVTQN  
61%ꢁ 61%ꢂ  
1WVRWV  
6+(ꢂꢅꢄ6KOGTꢄ+PVGTTWRVꢄ(NCIꢄꢂꢄꢌ$KVꢄꢈꢍꢆꢄWhen 6/&4ꢀ dec-  
rements to0, 6+(ꢀ is set to 1. This condition generates an  
interrupt request if enabled by 6+'ꢀꢅꢐ 1. 6+(ꢀ is reset to0  
when 6%4 is read and the higher or lower byte of 6/&4ꢀ  
is read. During 4'5'6, 6+(ꢀ is cleared to 0.  
+PJKDKVGF 6JGꢅ#ꢄꢆꢌ6  
ꢅRKPꢅKUꢅPQVꢅ  
CHHGEVGFꢅD[ꢅVJGꢅ246  
6QIINGF +HꢅDKVꢅꢍꢅQHꢅ+#4ꢄ$ꢅKUꢅꢄꢇꢅVJGꢅ  
#ꢄꢆꢌ6  
ꢅRKPꢅKUꢅVQIINGFꢅQTꢅ  
UGVꢅ.QYꢅQTꢅ*KIJꢅCUꢅ  
KPFKECVGF  
6+'ꢁꢅꢄ6KOGTꢄ+PVGTTWRVꢄ'PCDNGꢄꢁꢄꢌ$KVꢄꢑꢍꢆꢄWhen 6+'ꢀ is set  
to 1, 6+(ꢄꢅꢐ 1 generates a CPU interrupt request. When  
6+'ꢀ is reset to0, the interrupt request is inhibited. During  
4'5'6, 6+'ꢀ is cleared to 0.  
6&'ꢁꢎꢄꢂꢅꢄ6KOGTꢄ&QYPꢄ%QWPVꢄ'PCDNGꢄꢌ$KVUꢄꢁꢎꢄꢂꢍꢆꢄ6&'ꢄ  
and 6&'ꢀ enable and disable down-counting for 6/&4ꢄ  
and 6/&4ꢀ, respectively. When 6&'P (Pꢅꢐ ꢀ,) is set to  
1, down-counting is stopped and 6/&4P is freely read or  
written. 6&'ꢄ and 6&'ꢀ are cleared to0during 4'5'6 and  
6/&4P does not decrement until 6&'P is set to .  
61%ꢁꢎꢄꢂꢅꢄ6KOGTꢄ1WVRWVꢄ%QPVTQNꢄꢌ$KVUꢄꢋꢎꢄꢇꢍꢆꢄ61%ꢄ and  
61%ꢀ control the output of 246ꢄ using the multiplexed  
#ꢄꢆꢌ6  
pin as indicated in Table 12. During 4'5'6,  
61%ꢄ and 61%ꢀ are cleared to 0. If bit 3 of the +#4ꢄ$ reg-  
ister is 1, the 6  
function is selected. By programming  
ꢎꢆ  
2ꢅ4ꢅ'ꢅ.ꢅ+ꢅ/ꢅ+ꢅ0ꢅ#ꢅ4ꢅ;  
&5ꢀꢀꢁꢀꢀꢂꢃ</2ꢀꢂꢀꢀ  
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