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ZiLOG
#5%+ꢄ56#675ꢄ4')+56'4ꢄꢂꢎꢁ
Each ASCI channel status register (56#6ꢀꢇꢄ) allows inter-
rogation of ASCI communication, error and modem control
signal status, and the enabling or disabling of ASCI inter-
rupts.
#5%+ꢅ5VCVWUꢅ4GIKUVGTꢅꢀꢅꢈ56#6ꢀꢓꢅ+ꢌ1ꢅ#FFTGUUꢅꢐꢅꢀꢎ*ꢉ
ꢎ
$KV
$KV
ꢊ
ꢁ
ꢏ
ꢍ
ꢂ
ꢄ
ꢀ
2'
4
('
4
4'
6&4'
4
6+'
4&4( 1840
&%&ꢀ
4
4
4
4ꢌ9
4ꢌ9
#5%+ꢅ5VCVWUꢅ4GIKUVGTꢅꢄꢅꢈ56#6ꢄꢓꢅ+ꢌ1ꢅ#FFTGUUꢅꢐꢅꢀꢏ*ꢉ
ꢎ
ꢏ
ꢍ
ꢂ
ꢄ
ꢀ
ꢊ
ꢁ
4&4(
4
4'
2'
4
('
4
6&4'
4
6+'
1840
4
%65ꢄ'
4ꢌ9
4ꢌ9
4ꢌ9
(KIWTG ꢋꢑꢆ #5%+ꢄ5VCVWUꢄ4GIKUVGTU
4&4(ꢅꢄ4GEGKXGꢄ&CVCꢄ4GIKUVGTꢄ(WNNꢄꢌ$KVꢄꢐꢍꢆꢄ4&4( is set to
1 when an incoming data byte is loaded into an empty 4Z
(+(1. If a framing or parity error occurs, 4&4( is still set
and the receive data (which generated the error) is still load-
ed into the (+(1. 4&4( is cleared toꢅ0by reading 4&4 and
most recently received character in the (+(1 from +15612
mode, during 4'5'6 and for #5%+ꢀ if the &%&ꢀ input is
auto-enabled and is negated (High).
%06.# register is 1, a character is assembled in which the
parity does not match the 2'1 bit in the %06.$ register.
However, this status bit is not set until or unless the error
character becomes the oldest one in the 4Zꢅ(+(1. 2' is
cleared when software writes a 1 to the '(4 bit in the
%064.# register. 2' is also cleared by 4'5'6 in +15612
mode, or on #5%+ꢀ, if the &%&ꢀ pin is auto-enabled and is
negated (High).
1840ꢅꢄ1XGTTWPꢄ'TTQTꢄꢌ$KVꢄꢈꢍꢆꢄAn overrun condition oc-
curs if the receiver finishes assembling a character but the
4Zꢅ(+(1 is full so there is no room for the character. How-
ever, this status bit is not set until the most recent character
received before the overrun becomes the oldest byte in the
(+(1. This bit is cleared when software writes a 1 to the
'(4 bit in the %06.# register. The bit may also be cleared
by 4'5'6 in +15612 mode or #5%+ꢀ if the &%&ꢀ pin is
auto enabled and is negated (High).
('ꢅꢄ(TCOKPIꢄ'TTQTꢄꢌ$KVꢄꢉꢍꢆꢄA framing error is detected
when the stop bit of a character is sampled as ꢀꢌ52#%'.
However, this status bit is not set until/unless the error char-
acter becomes the oldest one in the 4Zꢅ(+(1. (' is cleared
when software writes a 1 to the '(4 bit in the %06.# reg-
ister. (' is also cleared by 4'5'6 in +15612 mode, or on
#5%+ꢀ, if the &%&ꢀ pin is auto-enabled and is negated
(High).
4'+ꢅꢄ4GEGKXGꢄ+PVGTTWRVꢄ'PCDNGꢄꢌ$KVꢄꢋꢍꢆꢄ4+' should be set to
1 to enable ASCI receive interrupt requests. When 4+' is
1, the Receiver requests an interrupt when a character is re-
ceived and 4&4( is set, but only if neither DMA channel
requires its request-routing field to be set to receive data
from this ASCI. That is, if 5/ꢄ ꢀ are ꢄꢄ and 5#4ꢄꢊ ꢄꢁ
are ꢄꢀ, or &+/ꢄ is 1 and +#4ꢄꢊ ꢄꢁ are ꢄꢀ, then ASCI1
does not request an interrupt for 4&4(. If 4+' is 1, either
ASCI requests an interrupt when 1840, 2' or (' is set, and
0QVGꢅ When an overrun occurs, the receiver does not place the
character in the shift register into the (+(1, nor any sub-
sequent characters, until the most recent good character
enters the top of the (+(1 so that 1840 is set. Software
then writes a 1 to '(4 to clear it.
2'ꢅꢄ2CTKV[ꢄ'TTQTꢄꢌ$KVꢄꢑꢍꢆꢄA parity error is detected when
parity checking is enabled.When the /1&ꢄ bit in the
ꢎꢎ
2ꢅ4ꢅ'ꢅ.ꢅ+ꢅ/ꢅ+ꢅ0ꢅ#ꢅ4ꢅ;
&5ꢀꢀꢁꢀꢀꢂꢃ</2ꢀꢂꢀꢀ
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