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ZiLOG
#5%+ꢄ4'%'+8'ꢄ4')+56'4
Register addresses 08Hand 09Hhold the ASCI receive data
for channel 0 and channel 1, respectively.
#5%+ꢄ4GEGKXGꢄ4GIKUVGTꢄ%JCPPGNꢄꢁ
/PGOQPKEꢄ4&4ꢁ
#FFTGUUꢄꢂꢏ*
#5%+ꢄ4GEGKXGꢄ4GIKUVGTꢄ%JCPPGNꢄꢂ
/PGOQPKEꢄ4&4ꢂ
#FFTGUUꢄꢂꢀ*
ꢂ
ꢊ
ꢁ
ꢏ
ꢎ
ꢍ
ꢄ
ꢀ
ꢂ
ꢊ
ꢁ
ꢏ
ꢎ
ꢍ
ꢄ
ꢀ
#5%+ꢅ6TCPUOKVꢅ&CVC
(KIWTG ꢋꢏꢆ #5%+ꢄ4GEGKXGꢄ4GIKUVGTꢄ%JCPPGNꢄꢁ
#5%+ꢅ6TCPUOKVꢅ&CVC
(KIWTG ꢋꢀꢆ #5%+ꢄ4GEGKXGꢄ4GIKUVGTꢄ%JCPPGNꢄꢂ
%5+ꢃ1ꢄ%10641.ꢃ56#675ꢄ4')+56'4
The CSI/O Control/Status Register (%064) is used to mon-
itor CSI/O status, enable and disable the CSI/O, enable and
disable interrupt generation, and select the data clock speed
and source.
ꢏ
ꢎ
ꢍ
ꢂ
ꢄ
ꢀ
$KV
ꢊ
ꢁ
AA
55ꢂ
4ꢌ9
55ꢄ
4ꢌ9
55ꢀ
4ꢌ9
ꢅ'(
4
'+'
4'
6'
4ꢌ9
4ꢌ9
4ꢌ9
(KIWTG ꢉꢂꢆ %5+ꢃ1ꢄ%QPVTQNꢄ4GIKUVGTꢄꢌ%064ꢅꢄ+ꢃ1ꢄ#FFTGUUꢄꢒꢄꢂꢂꢂ#*ꢍ
'(ꢅꢄ'PFꢄ(NCIꢄꢌ$KVꢄꢐꢍꢆꢄ'( is set to 1bytheCSI/O toindicate
completion of an 8-bit data transmit or receive operation.
If End Interrupt Enableꢅ('+') bit = 1 when '( is set to 1,
a CPU interrupt request is generated. Program access of
64&4 only occurs if'(ꢅꢐ 1. The CSI/O clears '( toꢅ0when
64&4 is read or written. '( is cleared toꢅ0during 4'5'6
and +15612 mode.
pin in synchronization with the (internal or external) data
clock. After receiving 8 bits of data, the CSI/O automati-
cally clears4' toꢅ0, '( isset to1, and an interrupt(ifenabled
by '+'ꢅꢐꢅꢄ) is generated. 4' and 6' are never both set to
1 at the same time. 4' is cleared toꢅ0during 4'5'6 and
+15612 mode.
6'ꢅꢄ6TCPUOKVꢄ'PCDNGꢄꢌ$KVꢄꢉꢍꢆꢄA CSI/O transmit operation
is started by setting 6' to 1. When 6' is set to 1, the data
clock is enabled. When in internal clock mode, the data
clock is output from the %-5 pin. In external clock mode,
the clock isinput on the %-5 pin. In either case, data is shift-
ed out on the 6:5 pin synchronous with the (internal or ex-
ternal) data clock. After transmitting 8 bits of data, the
CSI/O automatically clears 6' toꢅ0, sets '( to 1, and re-
quests an interrupt if enabled by '+'ꢅꢐ 1. 6' and 4' are
'+'ꢅꢄ'PFꢄ+PVGTTWRVꢄ'PCDNGꢄꢌ$KVꢄꢈꢍꢆꢄ'+' is set to 1 to gen-
erate a CPU interrupt request. The interrupt request is in-
hibited if '+' is reset to 0. '+' is cleared toꢅ0during 4'5'6.
4'ꢅꢄ4GEGKXGꢄ'PCDNGꢄꢌ$KVꢄꢑꢍꢆꢄA CSI/O receive operation is
started by setting 4' to 1. When 4' is set to 1, the data clock
is enabled. In internal clock mode, the data clock is output
from the %-5 pin. In external clock mode, the clock is input
on the %-5 pin. In either case, data is shifted in on the4:5
ꢎꢁ
2ꢅ4ꢅ'ꢅ.ꢅ+ꢅ/ꢅ+ꢅ0ꢅ#ꢅ4ꢅ;
&5ꢀꢀꢁꢀꢀꢂꢃ</2ꢀꢂꢀꢀ
ZILOG [ ZILOG, INC. ]
