Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!®
196
Table 126. eZ8 CPU Instruction Summary (Continued)
Assembly
Address Mode
Flags
Opcode(s)
(Hex)
Fetch Instr.
H Cycles Cycles
Mnemonic
Symbolic Operation
dst
src
ER
ER
IRR
IRR
X(rr)
r
C
Z
S
V
D
LDX dst, src
dst ← src
r
84
85
86
87
88
89
94
95
96
97
E8
E9
98
99
F4
-
-
-
-
-
-
3
3
3
3
3
3
3
3
3
3
4
4
3
3
2
2
3
4
5
4
4
2
3
4
5
2
2
3
5
8
Ir
R
IR
r
X(rr)
ER
ER
IRR
IRR
ER
ER
r
r
Ir
R
IR
ER
IM
X(r)
X(rr)
LEA dst, X(src)
MULT dst
dst ← src + X
-
-
-
-
-
-
-
-
-
-
-
-
rr
dst[15:0] ←
RR
dst[15:8] * dst[7:0]
NOP
No operation
0F
42
43
44
45
46
47
48
49
-
-
-
-
-
-
-
-
-
1
2
2
3
3
3
3
4
4
2
3
4
3
4
3
4
3
3
OR dst, src
dst ← dst OR src
r
r
r
*
*
0
Ir
R
R
R
IR
IM
IM
ER
IM
R
IR
ER
ER
ORX dst, src
dst ← dst OR src
-
*
*
0
-
-
0 = Reset to 0
1 = Set to 1
Flags Notation:
* = Value is a function of the result of the operation.
- = Unaffected
X = Undefined
PS017610-0404
eZ8 CPU Instruction Set
ZILOG [ ZILOG, INC. ]
