Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!®
197
Table 126. eZ8 CPU Instruction Summary (Continued)
Assembly
Address Mode
Flags
Opcode(s)
(Hex)
Fetch Instr.
H Cycles Cycles
Mnemonic
Symbolic Operation
dst
src
C
Z
S
V
D
POP dst
dst ← @SP
SP ← SP + 1
R
50
51
-
-
-
-
-
-
2
2
3
2
3
2
IR
ER
POPX dst
PUSH src
dst ← @SP
SP ← SP + 1
D8
-
-
-
-
-
-
-
-
-
-
-
-
SP ← SP – 1
@SP ← src
R
70
71
C8
2
2
3
2
3
2
IR
ER
PUSHX src
SP ← SP – 1
@SP ← src
-
-
-
-
-
-
RCF
RET
C ← 0
CF
AF
0
-
-
-
-
-
-
-
-
-
-
-
1
1
2
4
PC ← @SP
SP ← SP + 2
RL dst
R
90
91
*
*
*
*
-
-
2
2
2
3
C
D7 D6 D5 D4 D3 D2 D1 D0
dst
IR
RLC dst
RR dst
R
10
11
*
*
*
*
*
*
*
*
-
-
-
-
2
2
2
3
C
D7 D6 D5 D4 D3 D2 D1 D0
dst
IR
R
E0
E1
2
2
2
3
D7 D6 D5 D4 D3 D2 D1 D0
dst
C
IR
RRC dst
R
C0
C1
*
*
*
*
-
-
2
2
2
3
D7 D6 D5 D4 D3 D2 D1 D0
dst
C
IR
0 = Reset to 0
1 = Set to 1
Flags Notation:
* = Value is a function of the result of the operation.
- = Unaffected
X = Undefined
PS017610-0404
eZ8 CPU Instruction Set
ZILOG [ ZILOG, INC. ]
