Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!®
194
Table 126. eZ8 CPU Instruction Summary (Continued)
Assembly
Address Mode
Flags
Opcode(s)
(Hex)
Fetch Instr.
H Cycles Cycles
Mnemonic
Symbolic Operation
dst
src
C
Z
S
V
D
DA dst
dst ← DA(dst)
R
40
41
*
*
*
X
-
-
-
-
2
2
2
2
2
2
1
2
2
3
2
3
5
6
2
3
IR
DEC dst
dst ← dst - 1
R
30
-
-
*
*
*
*
*
*
-
-
IR
31
DECW dst
dst ← dst - 1
RR
IRR
80
81
DI
IRQCTL[7] ← 0
8F
-
-
-
-
-
-
-
-
-
-
-
-
DJNZ dst, RA
dst ← dst – 1
if dst ≠ 0
r
0A-FA
PC ← PC + X
EI
IRQCTL[7] ← 1
Halt Mode
9F
7F
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
1
2
2
1
2
2
1
2
2
2
3
2
5
6
5
HALT
INC dst
dst ← dst + 1
R
IR
r
20
*
*
*
21
0E-FE
A0
INCW dst
IRET
dst ← dst + 1
RR
IRR
-
*
*
*
*
*
*
-
-
A1
FLAGS ← @SP
SP ← SP + 1
PC ← @SP
BF
*
*
*
SP ← SP + 2
IRQCTL[7] ← 1
JP dst
PC ← dst
DA
IRR
DA
8D
C4
-
-
-
-
-
-
-
-
-
-
-
-
3
2
3
2
3
2
JP cc, dst
if cc is true
0D-FD
PC ← dst
JR dst
PC ← PC + X
DA
DA
8B
-
-
-
-
-
-
-
-
-
-
-
-
2
2
2
2
JR cc, dst
if cc is true
0B-FB
PC ← PC + X
0 = Reset to 0
1 = Set to 1
Flags Notation:
* = Value is a function of the result of the operation.
- = Unaffected
X = Undefined
PS017610-0404
eZ8 CPU Instruction Set
ZILOG [ ZILOG, INC. ]
