Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!®
195
Table 126. eZ8 CPU Instruction Summary (Continued)
Assembly
Address Mode
Flags
Opcode(s)
(Hex)
Fetch Instr.
H Cycles Cycles
Mnemonic
Symbolic Operation
dst
src
IM
X(r)
r
C
Z
S
V
D
LD dst, rc
dst ← src
r
0C-FC
C7
D7
E3
-
-
-
-
-
-
2
3
3
2
3
3
3
3
2
3
2
2
2
2
2
2
3
4
3
2
3
3
3
3
3
5
9
5
9
9
r
X(r)
r
Ir
R
R
E4
R
IR
IM
IM
r
E5
R
E6
IR
Ir
E7
F3
IR
r
R
F5
LDC dst, src
LDCI dst, src
dst ← src
Irr
Irr
r
C2
C5
D2
C3
D3
-
-
-
-
-
-
-
-
-
-
-
-
Ir
Irr
Ir
dst ← src
r ← r + 1
rr ← rr + 1
Irr
Ir
Irr
LDE dst, src
LDEI dst, src
dst ← src
r
Irr
r
82
92
83
93
-
-
-
-
-
-
-
-
-
-
-
-
2
2
2
2
5
5
9
9
Irr
Ir
dst ← src
r ← r + 1
rr ← rr + 1
Irr
Ir
Irr
0 = Reset to 0
1 = Set to 1
Flags Notation:
* = Value is a function of the result of the operation.
- = Unaffected
X = Undefined
PS017610-0404
eZ8 CPU Instruction Set
ZILOG [ ZILOG, INC. ]
