Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!®
198
Table 126. eZ8 CPU Instruction Summary (Continued)
Assembly
Address Mode
Flags
Opcode(s)
(Hex)
Fetch Instr.
H Cycles Cycles
Mnemonic
Symbolic Operation
dst
src
C
Z
S
V
D
SBC dst, src
dst ← dst – src - C
r
r
32
33
34
35
36
37
38
39
DF
D0
D1
*
*
*
*
1
*
2
2
3
3
3
3
4
4
1
2
2
3
4
3
4
3
4
3
3
2
2
3
r
Ir
R
R
R
IR
IM
IM
ER
IM
R
IR
ER
ER
SBCX dst, src
dst ← dst – src - C
C ← 1
*
*
*
*
1
*
SCF
1
*
-
-
-
-
-
-
-
SRA dst
R
*
*
0
D7 D6 D5 D4 D3 D2 D1 D0
dst
C
C
IR
SRL dst
R
1F C0
1F C1
*
*
0
*
-
-
3
3
2
3
0
D7 D6 D5 D4 D3 D2 D1 D0
dst
IR
SRP src
RP ← src
IM
01
6F
22
23
24
25
26
27
28
29
F0
F1
-
-
-
-
-
-
-
-
-
-
-
-
2
1
2
2
3
3
3
3
4
4
2
2
2
2
3
4
3
4
3
4
3
3
2
3
STOP
Stop Mode
dst ← dst – src
SUB dst, src
r
r
r
*
*
*
*
1
*
Ir
R
R
R
IR
IM
IM
ER
IM
R
IR
ER
ER
R
SUBX dst, src
SWAP dst
dst ← dst – src
*
*
*
*
*
*
1
-
*
-
dst[7:4] ↔ dst[3:0]
X
X
IR
0 = Reset to 0
1 = Set to 1
Flags Notation:
* = Value is a function of the result of the operation.
- = Unaffected
X = Undefined
PS017610-0404
eZ8 CPU Instruction Set
ZILOG [ ZILOG, INC. ]
