Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!®
200
Table 126. eZ8 CPU Instruction Summary (Continued)
Assembly
Address Mode
Flags
Opcode(s)
(Hex)
Fetch Instr.
H Cycles Cycles
Mnemonic
Symbolic Operation
dst
src
C
Z
S
V
D
XOR dst, src
dst ← dst XOR src
r
r
B2
B3
B4
B5
B6
B7
B8
B9
-
*
*
0
-
-
2
2
3
3
3
3
4
4
3
4
3
4
3
4
3
3
r
Ir
R
R
R
IR
IM
IM
ER
IM
R
IR
ER
ER
XORX dst, src
Flags Notation:
dst ← dst XOR src
-
*
*
0
-
-
0 = Reset to 0
1 = Set to 1
* = Value is a function of the result of the operation.
- = Unaffected
X = Undefined
PS017610-0404
eZ8 CPU Instruction Set