Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!®
192
Table 126. eZ8 CPU Instruction Summary (Continued)
Assembly
Address Mode
Flags
Opcode(s)
(Hex)
Fetch Instr.
H Cycles Cycles
Mnemonic
Symbolic Operation
dst
src
C
Z
S
V
D
ADD dst, src
dst ← dst + src
r
r
02
03
04
05
06
07
08
09
52
53
54
55
56
57
58
59
E2
E2
00
E2
D5
F6
F7
F6
F7
*
*
*
*
0
*
2
2
3
3
3
3
4
4
2
2
3
3
3
3
4
4
2
2
1
2
2
3
3
3
3
3
4
3
4
3
4
3
3
3
4
3
4
3
4
3
3
2
2
1
2
2
3
4
3
4
r
Ir
R
R
R
IR
IM
IM
ER
IM
r
R
IR
ER
ER
r
ADDX dst, src
AND dst, src
dst ← dst + src
*
-
*
*
*
*
*
0
0
-
*
-
dst ← dst AND src
r
Ir
R
R
R
IR
IM
IM
ER
IM
R
IR
ER
ER
r
ANDX dst, src
dst ← dst AND src
-
*
*
0
-
-
BCLR bit, dst
BIT p, bit, dst
BRK
dst[bit] ← 0
-
-
*
*
-
*
*
-
0
0
-
-
-
-
-
-
-
-
-
-
-
-
-
dst[bit] ← p
r
Debugger Break
dst[bit] ← 1
-
BSET bit, dst
BSWAP dst
r
-
*
*
-
*
*
-
0
0
-
dst[7:0] ← dst[0:7]
R
X
-
BTJ p, bit, src, dst if src[bit] = p
r
Ir
r
PC ← PC + X
BTJNZ bit, src, dst if src[bit] = 1
-
-
-
-
-
-
PC ← PC + X
Ir
0 = Reset to 0
1 = Set to 1
Flags Notation:
* = Value is a function of the result of the operation.
- = Unaffected
X = Undefined
PS017610-0404
eZ8 CPU Instruction Set
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