Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!®
199
Table 126. eZ8 CPU Instruction Summary (Continued)
Assembly
Address Mode
Flags
Opcode(s)
(Hex)
Fetch Instr.
H Cycles Cycles
Mnemonic
Symbolic Operation
dst
src
C
Z
S
V
D
TCM dst, src
(NOT dst) AND src
r
r
62
63
64
65
66
67
68
69
72
73
74
75
76
77
78
79
F2
-
*
*
0
-
-
2
2
3
3
3
3
4
4
2
2
3
3
3
3
4
4
2
3
4
3
4
3
4
3
3
3
4
3
4
3
4
3
3
6
r
Ir
R
R
R
IR
IM
IM
ER
IM
r
R
IR
ER
ER
r
TCMX dst, src
TM dst, src
(NOT dst) AND src
dst AND src
-
-
*
*
*
*
0
0
-
-
-
-
r
Ir
R
R
R
IR
IM
IM
ER
IM
Vector
R
IR
ER
ER
TMX dst, src
TRAP Vector
dst AND src
-
-
*
-
*
-
0
-
-
-
-
-
SP ← SP – 2
@SP ← PC
SP ← SP – 1
@SP ← FLAGS
PC ← @Vector
WDT
5F
-
-
-
-
-
-
1
2
0 = Reset to 0
1 = Set to 1
Flags Notation:
* = Value is a function of the result of the operation.
- = Unaffected
X = Undefined
PS017610-0404
eZ8 CPU Instruction Set
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