Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!®
191
Table 125. Rotate and Shift Instructions
Mnemonic
BSWAP
RL
Operands
dst
Instruction
Bit Swap
dst
Rotate Left
RLC
dst
Rotate Left through Carry
Rotate Right
RR
dst
RRC
dst
Rotate Right through Carry
Shift Right Arithmetic
Shift Right Logical
Swap Nibbles
SRA
dst
SRL
dst
SWAP
dst
eZ8 CPU Instruction Summary
Table 126 summarizes the eZ8 CPU instructions. The table identifies the addressing
modes employed by the instruction, the effect upon the Flags register, the number of CPU
clock cycles required for the instruction fetch, and the number of CPU clock cycles
required for the instruction execution.
.
Table 126. eZ8 CPU Instruction Summary
Address Mode
Flags
Assembly
Mnemonic
Opcode(s)
(Hex)
Fetch Instr.
H Cycles Cycles
Symbolic Operation
dst
r
src
r
C
Z
S
V
D
ADC dst, src
dst ← dst + src + C
12
13
14
15
16
17
18
19
*
*
*
*
0
*
2
2
3
3
3
3
4
4
3
4
3
4
3
4
3
3
r
Ir
R
R
R
IR
IM
IM
ER
IM
R
IR
ER
ER
ADCX dst, src
Flags Notation:
dst ← dst + src + C
*
*
*
*
0
*
0 = Reset to 0
1 = Set to 1
* = Value is a function of the result of the operation.
- = Unaffected
X = Undefined
PS017610-0404
eZ8 CPU Instruction Set
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