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Z8F082ASH020SC 参数 Datasheet PDF下载

Z8F082ASH020SC图片预览
型号: Z8F082ASH020SC
PDF下载: 下载PDF文件 查看货源
内容描述: Z8喝采XP -R F08xA系列与扩展外设 [Z8 Encore XP-R F08xA Series with eXtended Peripherals]
分类和应用: 微控制器和处理器外围集成电路光电二极管时钟
文件页数/大小: 244 页 / 2750 K
品牌: ZILOG [ ZILOG, INC. ]
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Z8 Encore! XP® F08xA Series  
Product Specification  
39  
Table 18. Port A–D Data Direction Sub-Registers (PxDD)  
BITS  
7
6
5
4
3
2
1
0
DD7  
DD6  
DD5  
DD4  
DD3  
DD2  
DD1  
DD0  
FIELD  
RESET  
R/W  
1
1
1
1
1
1
1
1
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
If 01H in Port A–D Address Register, accessible through the Port A–D Control Register  
ADDR  
DD[7:0]—Data Direction  
These bits control the direction of the associated port pin. Port Alternate Function opera-  
tion overrides the Data Direction register setting.  
0 = Output. Data in the Port A–D Output Data register is driven onto the port pin.  
1 = Input. The port pin is sampled and the value written into the Port A–D Input Data Reg-  
ister. The output driver is tristated.  
Port A–D Alternate Function Sub-Registers  
The Port A–D Alternate Function sub-register (Table 19) is accessed through the Port A–  
D Control register by writing 02Hto the Port A–D Address register. The Port A–D Alter-  
nate Function sub-registers enable the alternate function selection on pins. If disabled, pins  
functions as GPIO. If enabled, select one of four alternate functions using alternate func-  
tion set subregisters 1 and 2 as described in the “Port A–D Alternate Function Set 1 Sub-  
Registers” on page 42 and “Port A–D Alternate Function Set 2 Sub-Registers” on page 42.  
Refer to the “GPIO Alternate Functions” on page 32 to determine the alternate function asso-  
ciated with each port pin.  
Caution:  
Do not enable alternate functions for GPIO port pins for which there is no  
associated alternate function. Failure to follow this guideline can result in  
unpredictable operation.  
Table 19. Port A–D Alternate Function Sub-Registers (PxAF)  
BITS  
7
6
5
4
3
2
1
0
AF7  
AF6  
AF5  
AF4  
AF3  
AF2  
AF1  
AF0  
FIELD  
RESET  
R/W  
00H (Ports A–C); 01H (Port D)  
R/W  
If 02H in Port A–D Address Register, accessible through the Port A–D Control Register  
ADDR  
AF[7:0]—Port Alternate Function enabled  
0 = The port pin is in normal mode and the DDxbit in the Port A–D Data Direction sub-  
register determines the direction of the pin.  
PS024705-0405  
P R E L I M I N A R Y  
General-Purpose I/O