Z8 Encore! XP® F08xA Series
Product Specification
41
PHDE[7:0]—Port High Drive Enabled
0 = The Port pin is configured for standard output current drive.
1 = The Port pin is configured for high output current drive.
Port A–D STOP Mode Recovery Source Enable Sub-Registers
The Port A–D STOP Mode Recovery Source Enable sub-register (Table 22) is accessed
through the Port A–D Control register by writing 05Hto the Port A–D Address register.
Setting the bits in the Port A–D STOP Mode Recovery Source Enable sub-registers to 1
configures the specified Port pins as a STOP Mode Recovery source. During STOP Mode,
any logic transition on a Port pin enabled as a STOP Mode Recovery source initiates
STOP Mode Recovery.
Table 22. Port A–D STOP Mode Recovery Source Enable Sub-Registers (PxSMRE)
BITS
7
6
5
4
3
2
1
0
PSMRE7 PSMRE6 PSMRE5 PSMRE4 PSMRE3 PSMRE2 PSMRE1 PSMRE0
FIELD
RESET
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
If 05H in Port A–D Address Register, accessible through the Port A–D Control Register
ADDR
PSMRE[7:0]—Port STOP Mode Recovery Source Enabled
0 = The Port pin is not configured as a STOP Mode Recovery source. Transitions on this
pin during STOP mode do not initiate STOP Mode Recovery.
1 = The Port pin is configured as a STOP Mode Recovery source. Any logic transition on
this pin during STOP mode initiates STOP Mode Recovery.
Port A–D Pull-up Enable Sub-Registers
The Port A–D Pull-up Enable sub-register (Table 23) is accessed through the Port A–D
Control register by writing 06Hto the Port A–D Address register. Setting the bits in the
Port A–D Pull-up Enable sub-registers enables a weak internal resistive pull-up on the
specified Port pins.
Table 23. Port A–D Pull-Up Enable Sub-Registers (PxPUE)
BITS
7
6
5
4
3
2
1
0
PPUE7
PPUE6
PPUE5
PPUE4
PPUE3
PPUE2
PPUE1
PPUE0
FIELD
RESET
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
If 06H in Port A–D Address Register, accessible through the Port A–D Control Register
ADDR
PS024705-0405
P R E L I M I N A R Y
General-Purpose I/O
ZILOG [ ZILOG, INC. ]
