欢迎访问ic37.com |
会员登录 免费注册
发布采购

Z8F082ASH020SC 参数 Datasheet PDF下载

Z8F082ASH020SC图片预览
型号: Z8F082ASH020SC
PDF下载: 下载PDF文件 查看货源
内容描述: Z8喝采XP -R F08xA系列与扩展外设 [Z8 Encore XP-R F08xA Series with eXtended Peripherals]
分类和应用: 微控制器和处理器外围集成电路光电二极管时钟
文件页数/大小: 244 页 / 2750 K
品牌: ZILOG [ ZILOG, INC. ]
 浏览型号Z8F082ASH020SC的Datasheet PDF文件第56页浏览型号Z8F082ASH020SC的Datasheet PDF文件第57页浏览型号Z8F082ASH020SC的Datasheet PDF文件第58页浏览型号Z8F082ASH020SC的Datasheet PDF文件第59页浏览型号Z8F082ASH020SC的Datasheet PDF文件第61页浏览型号Z8F082ASH020SC的Datasheet PDF文件第62页浏览型号Z8F082ASH020SC的Datasheet PDF文件第63页浏览型号Z8F082ASH020SC的Datasheet PDF文件第64页  
Z8 Encore! XP® F08xA Series  
Product Specification  
42  
PPUE[7:0]—Port Pull-up Enabled  
0 = The weak pull-up on the Port pin is disabled.  
1 = The weak pull-up on the Port pin is enabled.  
Port A–D Alternate Function Set 1 Sub-Registers  
The Port A–D Alternate Function Set1 sub-register (Table 24) is accessed through the Port  
A–D Control register by writing 07Hto the Port A–D Address register. The Alternate  
Function Set 1 sub-registers selects the alternate function available at a port pin. Alternate  
Functions selected by setting or clearing bits of this register are defined in “GPIO Alternate  
Functions” on page 32.  
Alternate function selection on port pins must also be enabled as decribed in “Port A–D  
Note:  
Alternate Function Sub-Registers” on page 39.  
Table 24. Port A–D Alternate Function Set 1 Sub-Registers (PxAFS1)  
BITS  
7
6
5
4
3
2
1
0
PAFS17  
PAFS16  
PAFS15  
PAFS14  
PAFS13  
PAFS12  
PAFS11  
PAFS10  
FIELD  
RESET  
R/W  
0
0
0
0
0
0
0
0
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
If 07H in Port A–D Address Register, accessible through the Port A–D Control Register  
ADDR  
PAFS1[7:0]—Port Alternate Function Set 1  
0 = Port Alternate Function selected as defined in Table 13 in the GPIO Alternate Functions  
section.  
1 = Port Alternate Function selected as defined in Table 13 in the GPIO Alternate Functions  
section.  
Port A–D Alternate Function Set 2 Sub-Registers  
The Port A–D Alternate Function Set 2 sub-register (Table 25) is accessed through the  
Port A–D Control register by writing 08Hto the Port A–D Address register. The Alternate  
Function Set 2 sub-registers selects the alternate function available at a port pin. Alternate  
Functions selected by setting or clearing bits of this register is defined in Table 13 in the  
section “GPIO Alternate Functions” on page 32.  
Alternate function selection on port pins must also be enabled as decribed in “Port A–D  
Note:  
Alternate Function Sub-Registers” on page 39.  
Table 25. Port A–D Alternate Function Set 2 Sub-Registers (PxAFS2)  
BITS  
7
6
5
4
3
2
1
0
PAFS27  
PAFS26  
PAFS25  
PAFS24  
PAFS23  
PAFS22  
PAFS21  
PAFS20  
FIELD  
PS024705-0405  
P R E L I M I N A R Y  
General-Purpose I/O  
 复制成功!