Z8 Encore! XP® F08xA Series
Product Specification
35
Table 14. Port Alternate Function Mapping (Continued)(20/28-Pin Parts)
Alternate
Function Set
Register AFS1
Port
Pin
Mnemonic
Alternate Function Description
PB0
Reserved
AFS1[0]: 0
AFS1[0]: 1
AFS1[1]: 0
AFS1[1]: 1
AFS1[2]: 0
AFS1[2]: 1
AFS1[3]: 0
AFS1[3]: 1
AFS1[4]: 0
AFS1[4]: 1
AFS1[5]: 0
AFS1[5]: 1
AFS1[6]: 0
AFS1[6]: 1
AFS1[7]: 0
AFS1[7]: 1
Port B
ANA0/AMPOUT ADC Analog Input/Transamp Output
Reserved
PB1
PB2
PB3
PB4
PB5
PB6
PB7
ANA1/AMPINN
Reserved
ANA2/AMPINP
CLKIN
ADC Analog Input/Transamp Input (N)
ADC Analog Input/Transamp Input (P)
External Clock Input
ANA3
ADC Analog Input
Reserved
ANA7
ADC Analog Input
Reserved
VREF
ADC Voltage Reference
Reserved
Reserved
Reserved
Reserved
Note: Because there are at most two choices of alternate function for any pin of Port B, the Alternate
Function Set register AFS2 is implemented but not used to select the function. Also, alternate
function selection as described in “Port A–D Alternate Function Sub-Registers” on page 39 must
also be enabled.
PS024705-0405
P R E L I M I N A R Y
General-Purpose I/O
ZILOG [ ZILOG, INC. ]
