Z8 Encore! XP® F08xA Series
Product Specification
38
PADDR[7:0]—Port Address
The Port Address selects one of the sub-registers accessible through the Port Control reg-
ister.
PADDR[7:0] Port Control sub-register accessible using the Port A–D Control Registers
00H
01H
No function. Provides some protection against accidental Port reconfiguration.
Data Direction
02H
Alternate Function
03H
Output Control (Open-Drain)
High Drive Enable
04H
05H
STOP Mode Recovery Source Enable.
Pull-up Enable
06H
07H
Alternate Function Set 1
Alternate Function Set 2
No function
08H
09H–FFH
Port A–D Control Registers
The Port A–D Control registers set the GPIO port operation. The value in the correspond-
ing Port A–D Address register determines which sub-register is read from or written to by
a Port A–D Control register transaction (Table 17).
Table 17. Port A–D Control Registers (PxCTL)
BITS
7
6
5
4
3
2
1
0
PCTL
00H
FIELD
RESET
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FD1H, FD5H, FD9H, FDDH
ADDR
PCTL[7:0]—Port Control
The Port Control register provides access to all sub-registers that configure the GPIO Port
operation.
Port A–D Data Direction Sub-Registers
The Port A–D Data Direction sub-register is accessed through the Port A–D Control regis-
ter by writing 01H to the Port A–D Address register (Table 18).
PS024705-0405
P R E L I M I N A R Y
General-Purpose I/O
ZILOG [ ZILOG, INC. ]
