Z8 Encore! XP® F08xA Series
Product Specification
43
Table 25. Port A–D Alternate Function Set 2 Sub-Registers (PxAFS2)
0
0
0
0
0
0
0
0
RESET
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
If 08H in Port A–D Address Register, accessible through the Port A–D Control Register
ADDR
PAFS2[7:0]—Port Alternate Function Set 2
0 = Port Alternate Function selected as defined in Table 13 GPIO Alternate Functions sec-
tion.
1 = Port Alternate Function selected as defined in Table 13 GPIO Alternate Functions sec-
tion.
Port A–C Input Data Registers
Reading from the Port A–C Input Data registers (Table 26) returns the sampled values
from the corresponding port pins. The Port A–C Input Data registers are read-only. The
value returned for any unused ports is 0. Unused ports include those missing on the 8- and
28-pin packages, as well as those missing on the ADC-enabled 28-pin packages.
Table 26. Port A–C Input Data Registers (PxIN)
7
PIN7
X
6
PIN6
X
5
PIN5
X
4
PIN4
X
3
PIN3
X
2
PIN2
X
1
PIN1
X
0
PIN0
X
BITS
FIELD
RESET
R/W
R
R
R
R
R
R
R
R
FD2H, FD6H, FDAH
ADDR
PIN[7:0]—Port Input Data
Sampled data from the corresponding port pin input.
0 = Input data is logical 0 (Low).
1 = Input data is logical 1 (High).
Port A–D Output Data Register
The Port A–D Output Data register (Table 27) controls the output data to the pins.
Table 27. Port A–D Output Data Register (PxOUT)
BITS
7
6
5
4
3
2
1
0
POUT7
POUT6
POUT5
POUT4
POUT3
POUT2
POUT1
POUT0
FIELD
RESET
0
0
0
0
0
0
0
0
PS024705-0405
P R E L I M I N A R Y
General-Purpose I/O
ZILOG [ ZILOG, INC. ]
