Z8 Encore! XP® F08xA Series
Product Specification
37
GPIO Control Register Definitions
Four registers for each Port provide access to GPIO control, input data, and output data.
Table 15 lists these Port registers. Use the Port A–D Address and Control registers
together to provide access to sub-registers for Port configuration and control.
Table 15. GPIO Port Registers and Sub-Registers
Port Register Mnemonic
Port Register Name
PxADDR
Port A–D Address Register
(Selects sub-registers)
PxCTL
Port A–D Control Register
(Provides access to sub-registers)
PxIN
Port A–D Input Data Register
Port A–D Output Data Register
PxOUT
Port Sub-Register Mnemonic
Port Register Name
PxDD
PxAF
Data Direction
Alternate Function
PxOC
Output Control (Open-Drain)
High Drive Enable
PxHDE
PxSMRE
PxPUE
PxAFS1
PxAFS2
STOP Mode Recovery Source Enable
Pull-up Enable
Alternate Function Set 1
Alternate Function Set 2
Port A–D Address Registers
The Port A–D Address registers select the GPIO Port functionality accessible through the
Port A–D Control registers. The Port A–D Address and Control registers combine to pro-
vide access to all GPIO Port controls (Table 16).
Table 16. Port A–D GPIO Address Registers (PxADDR)
BITS
7
6
5
4
3
2
1
0
PADDR[7:0]
00H
FIELD
RESET
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FD0H, FD4H, FD8H, FDCH
ADDR
PS024705-0405
P R E L I M I N A R Y
General-Purpose I/O
ZILOG [ ZILOG, INC. ]
