Z8018x Family
MPU User Manual
298
Table 57. Internal I/O Registers (Continued)
Mnemonics Address
Register
Remarks
Timer Data Register
Channel 1L:
Timer Data Register
Channel 1H:
Timer Reload Register
Channel 1L
Timer Reload Register
Channel 1H:
TMDR1L
TMDR1H
RLDR1L
RLDR1H
1
1
1
1
4
5
6
7
Free Running Counter:
DMA Source Address
Register Channel 0L:
DMA Source Address
Register Channel 0H:
DMA Source Address
Register Channel 0B:
DMA Destination Address DAR0L
Register Channel 0L:
DMA Destination Address DAR0H
Register Channel 0H:
DMA Destination Address DAR0B
Register Channel 0B:
DMA Byte Count Register BCROL
Channel 0L:
DMA Byte Count Register BCROH
Channel 0H:
DMA Memory Address
Register
FRC
SAR0L
1
2
8
0
Read only
SAR0H
SAR0B
2
2
2
2
2
2
2
2
1
2
3
4
5
6
7
8
Bits 0-2 (3) are used for SAR0B
DMA Transfer Request
A19*, A18
,
A17
,
A16
X
X
X
X
X
X
X
X
0
0
1
1
0
1
0
1
DREQ0 (external)
RDR0 (ASCI0)
RDR1 (ASCI1)
Not used
Bits 0-2 (3) are used for DAR0B
DMA Transfer Request
A19*, A18
,
A17
,
A16
X
X
X
X
X
X
X
X
0
0
1
1
0
1
0
1
DREQ0 (external)
TDR0 (ASCI0)
TDR1 (ASCI1)
Not used
MAR1L
MAR1H
Channel 1L:
DMA Memory Address
Register
2
9
Channel 1H:
* In the R1 and Z mask, these DMAC registers are expanded from 4 bits to 3 bits in the
package version of CP-68.
UM005001-ZMP0400
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