Z8018x Family
MPU User Manual
297
Table 57. Internal I/O Registers (Continued)
Mnemonics Address
Register
Remarks
CSI/O Transmit/
Receive Data Register:
TRDR
0
0
0
0
0
1
B
C
D
E
F
Timer Data Register
Channel 0L:
TMDR0L
TMDR0H
RLDR0L
RLDR0H
TCR
Timer Data Register
Channel 0H:
Timer Reload Register
Channel 0L:
Timer Reload Register
Channel 0H:
TDE1
0
TF1
0
TF0
TE1
0
TE0 TOC1 TOC0
TDE0
0
Timer Control Register
Channel 0L:
0
bit
0
0
0
0
during RESET
R/W
R
R
R/W
R/W
R/W
R/W R/W
R/W
Timer Down
Count Enable 1,0
Timer Output Control 1,0
Timer Interrupt Enable 1,0
Timer Interrupt Flag 1,0
A18/TOUT
Inhibited
Toggle
0
1
TOC1,0
0 0
0 1
1 0
1 1
UM005001-ZMP0400
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