Z8018x Family
MPU User Manual
295
Table 57. Internal I/O Registers (Continued)
Mnemonics Address
Register
Remarks
ASCI Status Channel 0:
STAT0
0
4
RDRF OVRN PE
FE
RIE
DCD0 TDRE
TIE
bit
during RESET
R/W
0
0
0
0
invalid
R/W
*
**
R
0
R
R
R
R
R
R/W
Transmit Interrupt Enable
Transmit Data Register Empty
Data Carrier Detect
Receive Interrupt Enable
Framing Error
Parity Error
Overrun Error
Receive Data Register Full
TDRE
1
** CTS0 Pin
L
0
* DCD0: Depending on the condition ofDCD0 Pin.
H
ASCI Status Channel 1:
STAT1
0
5
CTS1E
RDRF OVRN PE
FE
RIE
TDRE
TIE
bit
during RESET
R/W
0
0
0
0
0
0
1
0
R
R
R
R
R
R
R/W
R/W
Transmit Interrupt Enable
Transmit Data Register Empty
CTS1Enable
Receive Interrupt Enable
Framing Error
Parity Error
Overrun Error
Receive Data Register Full
UM005001-ZMP0400
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