Z8018x Family
MPU User Manual
301
Table 57. Internal I/O Registers (Continued)
Mnemonics Address
Register
Remarks
DMA/WAIT Control
Register:
DCNTL
3
2
DIMA1
0
MWI1 MWI0
IWI1
1
IWI0 DMS1 DMS0
DIMA0
0
bit
1
1
1
0
0
during RESET
R/W
R/W
R/W
R/W
R/W
R/W
R/W R/W
R/W
DMA Ch 1
I/O Memory
Mode Select
DREQi Select, i=1,0
I/O Wait Insertion
Memory Wait Insertion
The number of
wait states
The number of
wait states
MWI1,0
IWI1,0
0
1
2
3
0
2
3
4
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
Sense
DMSi
1
0
Edge sense
Level sense
Transfer Mode Address Increment/Decrement
DIM1,0
M
M
I/O
® I/O
® I/O
M
AR1+1
I
I
M
M
AR1 fixed
AR1 fixed
AR1+1
AR1-1
0 0
0 1
1 0
1 1
MAR1-1
I
I
AR1 fixed
AR1 fixed
®
M
M
I/O
®
UM005001-ZMP0400
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