Z8018x Family
MPU User Manual
294
Table 57. Internal I/O Registers (Continued)
Mnemonics Address
Register
Remarks
ASCI Control Register B CNTLB0
Channel 0:
0
2
CTS/
SS1
MP
SS0
MPBT
PEO
PS
SS2
DR
0
bit
invalid
R/W
1
1
during RESET
R/W
1
0
0
R/W
*
R/W
R/W
R/W
R/W
R/W
R/W
Clock Source and
Speed Select
Divide Ratio
Parity Even or Odd
Clear to send/Prescale
Multi Processor
Multi Processor Bit Transmit
* CTS: Depending on the condition 0fCTS Pin.
PS: Cleared to 0.
ASCI Control Register B CNTLB1
Channel 1:
0
3
CTS/
MPBT
MP
PEO
DR
SS2
SS1
SS0
bit
PS
during RESET
R/W
invalid
R/W
0
0
0
0
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Clock Source and
Speed Select
Divide Ratio
Parity Even or Odd
Clear to Send/Prescale
Multi Processor
Multi Processor Bit Transmit
PS=0
(divide ratio=10)
PS=1
(divide ratio=30)
General
divide ratio
SS2 1 0
DR=0 (X 16)
DR=1 (X 64)
DR=0 (X 16) DR=1 (X 64)
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
480
160
f
¸
¸
f
¸
¸
¸
¸
¸
¸
¸
640
1280
2560
5120
10240
f
¸
¸
¸
¸
¸
¸
1920
3840
7680
15360
f
¸
¸
¸
¸
¸
¸
960
1920
3840
320
640
1280
2560
5120
¸
¸
¸
¸
7680
15360
30720
61440
20480
40960
¸
¸
¸
122880
10240
30720
1 1 1
External clock (frequency <f ¸ 40)
UM005001-ZMP0400
ZILOG [ ZILOG, INC. ]
