Z8018x Family
MPU User Manual
302
Table 57. Internal I/O Registers (Continued)
Mnemonics Address
Register
Remarks
Interrupt Vector Low
Register
IL
3
3
IL7
0
—
0
IL6
0
IL5
0
—
0
—
0
—
0
—
0
bit
during RESET
R/W
R/W
R/W
R/W
Interrupt Vector Low
INT/TRAP Control
Register
ITC
3
4
TRAP
0
UF0
0
—
1
—
1
—
1
ITE2
0
ITE1
0
ITE0
0
bit
during RESET
R/W
R
R/W
R/W
R/W
R/W
INT Enable 2,1,0
Unidentified Fetch Object
TRAP
REFE
1
—
1
—
1
—
1
—
1
REFW
1
CYC1 CYC0
Refresh Control Register: RCR
3
6
bit
0
0
during RESET
R/W
R/W
R/W
R/W
R/W
Cycle select
Refresh Wait State
Refresh Enable
Interval of Refresh Cycle
10 states
0 0
0 1
1 0
1 1
20
40
80
UM005001-ZMP0400
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