Z8018x Family
MPU User Manual
299
Table 57. Internal I/O Registers (Continued)
Mnemonics Address
Register
Remarks
DMA Memory Address
Register
MAR1B
2
A
Bits 0 - 2 are used for MAR1B
Channel 1B:
DMA I/O Address Register IAR1L
Channel 1L:
2
2
2
B
C
DMA I/O Address Register IAR1H
Channel 1H
DMA Byte Count Register BCR1L
Channel 1L:
E
DMA Byte Count Register
Channel 1H:
BCR1H
DSTAT
2
3
F
0
DMA Status Register:
DE1
0
DE0 DWE1 DWE0 DIE1
R/W
DIE0
—
1
DME
bit
during RESET
R/W
0
1
1
0
0
0
R/W
W
W
R/W
R
R/W
DMA Master enable
DMA Interrupt Enable 1,0
DMA Enable Bit Write Enable 1,0
DMA enable ch 1,0
DMA Mode Register:
DMODE
3
1
—
1
—
DM1
DM0 SM1
SM0 MMOD
—
1
bit
during RESET
R/W
1
0
0
0
0
0
R/W
R/W R/W
R/W
R/W
Memory MODE select
Ch 0 Source Mode 1,0
Ch 0 Destination Mode 1,0
Source
DM1,0
Destination
M
SM1,0
Address
Address
M
M
M
I/O
0 0
0 1
1 0
1 1
0
0
1
0
1
0
DAR0+1
SAR0+1
M
M
I/O
DAR0-1
SAR0-1
DAR0 fixed
DAR0 fixed
SAR0 fixed
SAR0 fixed
1 1
MMOD
Mode
Cycle Steal Mode
Burst Mode
0
1
UM005001-ZMP0400
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