Z8018x Family
MPU User Manual
300
Table 57. Internal I/O Registers (Continued)
Mnemonics Address
Register
Remarks
MMU Common Base
Register:
CBR
3
3
3
8
CB7
0
CB6
0
CB5
0
CB4
0
CB3
0
CB2
0
CB1
0
CB0
0
bit
during RESET
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
MMU Common Base Register
MMU Bank Base Register BBR
9
BB7
0
BB6
0
BB5
0
BB4
0
BB3
0
BB2
0
BB1
0
BB0
0
bit
during RESET
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
MMU Bank Base Register
MMU Common/Bank
Register
CBAR
A
CA3
1
CA2
1
CA1
1
CA0
1
BA3
0
BA2
0
BA1
0
BA0
0
bit
during RESET
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
MMU Bank
Area Register
MMU Common Area Register
Operation Mode Control
Register
OMCR
3
3
E
F
MIE
1
MITE
1
IOC
—
1
—
1
—
1
—
1
—
1
bit
1
during RESET
R/W
W
R/W
R/W
I/O Compatibility
M1 Temporary Enable
M1 Enable
I/O Control Register:
ICR
IOA7
0
—
1
—
1
IOA6 IOSTP
—
1
—
—
1
bit
0
0
1
during RESET
R/W
R/W
R/W
R/W
I/O Stop
I/O Address
UM005001-ZMP0400
ZILOG [ ZILOG, INC. ]
