eZ80L92 MCU
Product Specification
46
Table 12. Vectored Interrupt Operation (Continued)
Memory
Mode
ADL MADL
Bit
Bit Operation
0 Read the LSB of the interrupt vector placed on the internal vectored
interrupt bus, IVECT [7:0], by the interrupting peripheral.
ADL Mode
1
•
•
•
•
•
•
•
•
•
IEF1 ← 0
IEF2 ← 0
The starting Program Counter is PC[23:0].
Push the 3-byte return address, PC[23:0], onto the SPL stack.
The ADL mode bit remains set to 1.
The interrupt vector address is located at { 00h, I[7:0], IVECT[7:0] }.
PC[15:0] ← ( { 00h, I[7:0], IVECT[7:0] } ).
The ending Program Counter is { 00h, PC[15:0] }.
The interrupt service routine must end with RETI.
Z80 Mode
0
1
Read the LSB of the interrupt vector placed on the internal vectored
interrupt bus, IVECT[7:0], bus by the interrupting peripheral.
•
•
•
•
•
IEF1 ← 0
IEF2 ← 0
The starting Program Counter is effectively {MBASE, PC[15:0]}.
Push the 2-byte return address, PC[15:0], onto the SPL stack.
®
Push a 00h byte onto the SPL stack to indicate an interrupt from Z80
mode (because ADL = 0).
•
•
•
•
•
Set the ADL mode bit to 1.
The interrupt vector address is located at { 00h, I[7:0], IVECT[7:0] }.
PC[15:0] ← ( { 00h, I[7:0], IVECT[7:0] } ).
The ending Program Counter is { 00h, PC[15:0] }.
The interrupt service routine must end with RETI.L
PS013015-0316
Interrupt Controller
ZILOG [ ZILOG, INC. ]
