eZ80L92 MCU
Product Specification
50
Table 13. Register Values for Memory Chip Select Example in Figure 4
Chip
CSx_CTL[3] CSx_CTL[4]
Select
CSx_EN
CSx_IO
CSx_LBR CSx_UBR Description
CS0
CS1
CS2
CS3
1
0
00h
00h
A0h
D0h
7Fh
9Fh
CFh
FFh
CS0 is enabled as a Memory Chip Select.
Valid addresses range from
000000h–7FFFFFh.
1
1
1
0
0
0
CS1 is enabled as a Memory Chip Select.
Valid addresses range from
800000h–9FFFFFh.
CS2 is enabled as a Memory Chip Select.
Valid addresses range from
A00000h–CFFFFFh.
CS3 is enabled as a Memory Chip Select.
Valid addresses range from
D00000h–FFFFFFh.
I/O Chip Select Operation
I/O Chip Selects are active when the CPU is performing I/O instructions. As the I/O space
is separate from the memory space in the ZLP12840 device, there can never be a conflict
between I/O and memory addresses.
The ZLP12840 MCU supports a 16-bit I/O address. The I/O Chip Select logic decodes the
High byte of the I/O address, ADDR[15:8]. Because the upper byte of the address bus,
ADDR[23:16], is ignored, the I/O devices is always accessed from within any memory
mode (ADL or Z80). The MBASE offset value used for setting the Z80 MEMORY mode
page is also always ignored.
Four I/O Chip Selects are available with the ZLP12840. To generate a particular I/O Chip
Select, the following conditions must be fulfilled:
•
•
•
•
•
The Chip Select is enabled by setting CSX_EN to 1.
The Chip Select is configured for I/O by setting CSx_IO to 1.
An I/O Chip Select address match occurs—ADDR[15:8] = CSx_LBR[7:0].
No higher-priority (lower-number) Chip Select meets the above conditions.
The I/O address is not within the on-chip peripheral address range 0080h–00FFh. On-
chip peripheral registers assume priority for all addresses where:
0080h
≤ ADDR[15:0] ≤ 00FFh
•
An I/O instruction must be executing.
PS013015-0316
Chip Selects and Wait States
ZILOG [ ZILOG, INC. ]
