eZ80L92 MCU
Product Specification
43
Port x Data Direction Registers
In addition to the other GPIO Control Registers, the Port x Data Direction Registers (see
Table 8) control the operating modes of the GPIO port pins. See Table 6.
Table 8. Port x Data Direction Registers (PB_DDR = 009Bh, PC_DDR =
009Fh, PD_DDR = 00A3h)
Bit
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
1
Reset
CPU Access
Note: R/W = Read/Write.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Port x Alternate Register 1
In addition to other GPIO Control Registers, the Port x Alternate Register 1 (see Table 9)
control the operating modes of the GPIO port pins. See Table 6.
Table 9. Port x Alternate Registers 1 (PB_ALT1 = 009Ch, PC_ALT1 = 00A0h,
PD_ALT1 = 00A4h)
Bit
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Reset
CPU Access
Note: R/W = Read/Write.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Port x Alternate Register 2
In addition to other GPIO Control Registers, the Port x Alternate Register 2 (see Table 10)
control the operating modes of the GPIO port pins. See Table 6.
Table 10. Port x Alternate Registers 2 (PB_ALT2 = 009Dh, PC_ALT2 =
00A1h, PD_ALT2 = 00A5h)
Bit
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Reset
CPU Access
Note: R/W = Read/Write.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PS013015-0316
General-Purpose Input/Output
ZILOG [ ZILOG, INC. ]
